850 resultados para Architectural reuse
Resumo:
Wastewater is reused and treated in four main types of farming in Vietnam: fish culture in 200 ha; rotation of rice and fish culture in 400 ha; land vegetables and aquatic vegetables.
Resumo:
This paper advances the proposition that in many electronic products, the partitioning scheme adopted and the interconnection system used to interconnect the sub-assemblies or components are intimately related to the economic benefits, and hence the attractiveness, of reuse of these items. An architecture has been developed in which the residual values of the connectors, components and sub-assemblies are maximized, and opportunities for take-back and reuse of redundant items are greatly enhanced. The system described also offers significant manufacturing cost benefits in terms of ease of assembly, compactness and robustness.
Resumo:
Like the Research Assessment Exercise (RAE) that preceded it, the UK government's proposed Research Excellence Framework (REF) is a means of allocating funding in higher education to support research. As with any method for the competitive allocation of funds it creates winners and losers and inevitably generates a lot of emotion among those rewarded or penalised. More specifically, the 'winners' tend to approve of the method of allocation and the 'losers' denigrate it as biased against their activities and generally unfair. An extraordinary press campaign has been consistently waged against research assessment and its methods by those involved in architectural education, which I will track over a decade and a half. What follows will question whether this campaign demonstrates the sophistication and superior judgment of those who have gone into print, or conversely whether its mixture of misinformation and disinformation reveals not just disenchantment and prejudice, but a naivety and a depth of ignorance about the fundamentals of research that is deeply damaging to the credibility of architecture as a research-based discipline. With the recent consultation process towards a new cycle of research assessment, the REF, getting under way, I aim to draw attention to the risk of repeating past mistakes. Copyright © Cambridge University Press 2010.
Resumo:
Pile reuse has become an increasingly popular option in foundation design, mainly due to its potential cost and environmental benefits and the problem of underground congestion in urban areas. However, key geotechnical concerns remain regarding the behavior of reused piles and the modeling of foundation systems involving old and new piles to support building loads of the new structure. In this paper, a design and analysis tool for pile reuse projects will be introduced. The tool allows coupling of superstructure stiffness with the foundation model, and includes an optimization algorithm to obtain the best configuration of new piles to work alongside reused piles. Under the concept of Pareto Optimality, multi-objective optimization analyses can also reveal the relationship between material usage and the corresponding foundation performance, providing a series of reuse options at various foundation costs. The components of this analysis tool will be discussed and illustrated through a case history in London, where 110 existing piles are reused at a site to support the proposed new development. The case history reveals the difficulties faced by foundation reuse in urban areas and demonstrates the application of the design tool to tackle these challenges. © ASCE 2011.
Resumo:
This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.