On-line Estimation of Fundamental and Ripple Components of Line Currents in a Voltage-Source Inverter Operated at Low Switching Frequency

High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

Space vector based modulation scheme for reducing capacitor RMS current in three-level diode-clamped inverter

The DC capacitor is an important component in a voltage source inverter.The RMS current flowing through the capacitor determines the capacitor size and losses. The losses, in turn, influence the capacitor life. This paper proposes a space vector based modulation strategy for reducing the capacitor RMS current in a three-level diode-clamped inverter. An analytical closed-form expression is derived for the DC capacitor RMS current with the proposed PWM strategy. The analytical expression is validated through simulations and also experimentally. Theoretical and experimental results are presented, comparing the proposed strategy with conventional space vector PWM (CSVPWM). It is shown that the proposed strategy reduces the capacitor RMS current significantly at high modulation indices and high power factors. (C) 2014 Elsevier B.V. All rights reserved.

Small-Signal Stability Analysis of an Open-loop Induction Motor Drive Including the Effect of Inverter Dead-Time

This paper demonstrates light-load instability in open-loop induction motor drives on account of inverter dead-time. The dynamic equations of an inverter fed induction motor, incorporating the effect of dead-time, are considered. A procedure to derive the small-signal model of the motor, including the effect of inverter dead-time, is presented. Further, stability analysis is carried out on a 100-kW, 415V, 3-phase induction motor considering no-load. For voltage to frequency (i.e. V/f) ratios between 0.5 and 1 pu, the analysis brings out regions of instability on the V-f plane, in the frequency range between 5Hz and 20Hz. Simulation and experimental results show sub-harmonic oscillations in the motor current in this region, confirming instability as predicted by the analysis.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Optimal Pulse Width Modulation of Voltage-Source Inverter fed Motor Drives with Relaxation of Quarter Wave Symmetry Condition

Optimal switching angles for minimization of total harmonic distortion of line current (I-THD) in a voltage source inverter are determined traditionally by imposing half-wave symmetry (HWS) and quarter-wave symmetry (QWS) conditions on the pulse width modulated waveform. This paper investigates optimal switching angles with QWS relaxed. Relaxing QWS expands the solution space and presents the possibility of improved solutions. The optimal solutions without QWS are shown here to outperform the optimal solutions with QWS over a range of modulation index (M) between 0.82 and 0.94 for a switching frequency to fundamental frequency ratio of 5. Theoretical and experimental results are presented on a 2.3kW induction motor drive.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

Experimental Study on Switching Characteristics of an Inverter Leg Consisting of IGBTs of Dissimilar Makes

Usually the top and bottom IGBT devices in an inverter leg are of the same make (i.e. from same manufacturer). At low power level, these two devices even may be contained in the same module. However at high power levels the top and bottom devices are in separate modules. Sometimes, in the event of device failure, device of particular make may be replaced by one of another make, but of same ratings (on account of non-availability of the original make). This paper investigates the effect of such intermixing of two different makes of high power IGBTs in an inverter leg on the switching characteristics. The switching transitions between IGBT and diode of similar make and those of IGBT and diode of dissimilar make are compared experimentally at various DC link voltages and currents. The comparisons are made in terms of, IGBT peak turn-on di/dt, IGBT peak turn-off di/dt, peak diode reverse recovery current (I-rr), peak IGBT voltage overshoot and switching energy losses.

High Performance Modulation of High-Frequency AC Link Inverter

Inverters with high voltage conversion ratio are used in systems with sources such as batteries, photovoltaic (PV) modules or fuel cells. Transformers are often used in such inverters to provide the required voltage conversion ratio and isolation. In this paper, a compact high-frequency (HF) transformer interfaced AC link inverter with lossless snubber is discussed. A high performance synchronized modulation scheme is proposed for this inverter. This modulation addresses the issue of over-voltage spikes due to transformer leakage inductance and it is shown that the circuit can operate safely even when the turn-on delay, such as dead-time, is not used in the HF rectifier section. The problem of spurious turn-on in the HF inverter switches is also mitigated by the proposed modulation method. The circuit performance is validated experimentally with a $900W$ prototype inverter.

Small-Signal Stability Analysis of an Open-Loop Induction Motor Drive Including the Effect of Inverter Deadtime

This paper demonstrates light-load instability in a 100-kW open-loop induction motor drive on account of inverter deadtime. An improved small-signal model of an inverter-fed induction motor is proposed. This improved model is derived by linearizing the nonlinear dynamic equations of the motor, which include the inverter deadtime effect. Stability analysis is carried out on the 100-kW415-V three-phase induction motor considering no load. The analysis brings out the region of instability of this motor drive on the voltage versus frequency (V-f) plane. This region of light-load instability is found to expand with increase in inverter deadtime. Subharmonic oscillations of significant amplitude are observed in the steady-state simulated and measured current waveforms, at numerous operating points in the unstable region predicted, confirming the validity of the stability analysis. Furthermore, simulation and experimental results demonstrate that the proposed model is more accurate than an existing small-signal model in predicting the region of instability.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.

Evaluation and Minimization of Low-Order Harmonic Torque in Low-Switching-Frequency Inverter-Fed Induction Motor Drives

A low-order harmonic pulsating torque is a major concern in high-power drives, high-speed drives, and motor drives operating in an overmodulation region. This paper attempts to minimize the low-order harmonic torques in induction motor drives, operated at a low pulse number (i.e., a low ratio of switching frequency to fundamental frequency), through a frequency domain (FD) approach as well as a synchronous reference frame (SRF) based approach. This paper first investigates FD-based approximate elimination of harmonic torque as suggested by classical works. This is then extended into a procedure for minimization of low-order pulsating torque components in the FD, which is independent of machine parameters and mechanical load. Furthermore, an SRF-based optimal pulse width modulation (PWM) method is proposed to minimize the low-order harmonic torques, considering the motor parameters and load torque. The two optimal methods are evaluated and compared with sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experimental studies on a 3.7-kW induction motor drive. The SRF-based optimal PWM results in marginally better performance than the FD-based one. However, the selection of optimal switching angle for any modulation index (M) takes much longer in case of SRF than in case of the FD-based approach. The FD-based optimal solutions can be used as good starting solutions and/or to reasonably restrict the search space for optimal solutions in the SRF-based approach. Both of the FD-based and SRF-based optimal PWM methods reduce the low-order pulsating torque significantly, compared to ST PWM and SHE PWM, as shown by the simulation and experimental results.

Modelling and analysis of an open-loop induction motor drive incorporating the effect of inverter dead-time

The objective of this paper is to study the influence of inverter dead-time on steady as well as dynamic operation of an open-loop induction motor drive fed from a voltage source inverter (VSI). Towards this goal, this paper presents a systematic derivation of a dynamic model for an inverter-fed induction motor, incorporating the effect of inverter dead-time, in the synchronously revolving dq reference frame. Simulation results based on this dynamic model bring out the impact of inverter dead-time on both the transient response and steady-state operation of the motor drive. For the purpose of steady-state analysis, the dynamic model of the motor drive is used to derive a steady-state model, which is found to be non-linear. The steady-state model shows that the impact of dead-time can be seen as an additional resistance in the stator circuit, whose value depends on the stator current. Towards precise evaluation of this dead-time equivalent resistance, an analytical expression is proposed for the same in terms of inverter dead-time, switching frequency, modulation index and load impedance. The notion of dead-time equivalent resistance is shown to simplify the solution of the non-linear steady-state model. The analytically evaluated steady-state solutions are validated through numerical simulations and experiments.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.