A computationally efficient DAB bit-stream processor

This paper describes an MPEG (moving pictures expert group) audio layer II - LFE (lower frequency extension) bit-stream processor targeting DAB (digital audio broadcasting) receivers that will handle the decoding of the frames in a computationally efficient manner to provide a synthesis sub-band filter with the reconstructed sub-band samples. Focus is given to the frequency sample reconstruction part, which handles the re-quantization and re-scaling of the samples once the necessary information is extracted from the frame. The comparison to a direct implementation of the frequency sample reconstruction block is carried out to prove increased computational efficiency.

An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute a 256-point complex FFT in 102.4 μs excluding data input and output processes.

An integrated 256-point complex FFT processor for real-time spectrum analysis and measurement

This paper describes in detail the design of a custom CMOS Fast Fourier Transform (FFT) processor for computing 256-point complex FFT. The FFT is well suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute 256-complex point FFT in 25.6 μs excluding data input and output processes.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

Implementation of Multi-Core Processor Based on PLASMA (Most MIPS I) IP Core

Multi-core processors is a design philosophy that has become mainstream in scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices has permitted complex logic systems to be implemented on a single programmable device. By using VHDL here we present an implementation of one multi-core processor by using the PLASMA IP core based on the (most) MIPS I ISA and give an overview of the processor architecture and share theexecution results.

SCIL processor : a common intermediate language processor for embedded systems

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

A Concurrent Smalltalk Compiler for the Message-Driven Processor

This thesis describes Optimist, an optimizing compiler for the Concurrent Smalltalk language developed by the Concurrent VLSI Architecture Group. Optimist compiles Concurrent Smalltalk to the assembly language of the Message-Driven Processor (MDP). The compiler includes numerous optimization techniques such as dead code elimination, dataflow analysis, constant folding, move elimination, concurrency analysis, duplicate code merging, tail forwarding, use of register variables, as well as various MDP-specific optimizations in the code generator. The MDP presents some unique challenges and opportunities for compilation. Due to the MDP's small memory size, it is critical that the size of the generated code be as small as possible. The MDP is an inherently concurrent processor with efficient mechanisms for sending and receiving messages; the compiler takes advantage of these mechanisms. The MDP's tagged architecture allows very efficient support of object-oriented languages such as Concurrent Smalltalk. The initial goals for the MDP were to have the MDP execute about twenty instructions per method and contain 4096 words of memory. This compiler shows that these goals are too optimistic -- most methods are longer, both in terms of code size and running time. Thus, the memory size of the MDP should be increased.

Concurrent Smalltalk on the Message-Driven Processor

Concurrent Smalltalk is the primary language used for programming the J- Machine, a MIMD message-passing computer containing thousands of 36-bit processors connected by a very low latency network. This thesis describes in detail Concurrent Smalltalk and its implementation on the J-Machine, including the Optimist II global optimizing compiler and Cosmos fine-grain parallel operating system. Quantitative and qualitative results are presented.

Cervell, intel.ligències i dissenys d'ensenyament-aprenentatge. 'Cerebro, inteligencias y diseños de enseñanza-aprendizaje'

Se expone la diversidad de estilos cognitivos y de estilos de aprendizaje producto de los factores dominantes del funcionamiento del cerebro. El repaso, breve pero conciso, hace un recorrido por las partes del cerebro más desarrolladas en cuanto al aprendizaje se refiere. También proporciona pautas y metodologías de actuación en el aula para mejorar la enseñanza en el día a día, partiendo de una motivación y una emoción que los maestros deben transmitir a sus alumnos para obtener buenos resultados, tanto cognitivos como del propio desarrollo personal .

Avaluació de la intel.ligència a partir de tests de relacions lògiques. 'Evaluación de la inteligencia a partir de tests de relaciones lógicas'.

Crear dos tests de inteligencia basados en relaciones lógicas y evaluar su aplicación.. 60 niños de edades entre 13-14 años de escuelas públicas.. Realiza un análisis histórico y evolutivo del concepto inteligencia y conceptos relacionados (modelos, estructuras jerarquicas, procesos intelecturales, conducta, metacognición, estrategias de aprendizaje). Elabora dos test de inteligencia: el TRL-LI (test de relaciones lógicas con letras) y el TRL-F (test de relaciones lógicas con figuras). Depura estos dos instrumentos y realiza un estudio práctico donde se contrastan los dos tests. Factores analizados: razonamiento abstracto general, razonamiento abstracto a partir del AMPE, relaciones lógicas entre conjuntos y relaciones lógicas en complemento de estructuras complejas no verbales.. Test ad-hoc, RAVEN D-48, DAT-AR, PMA-R1, PMA-R3, AMPE-R1, AMPE-R3 . Medias, desviaciones standars, varianza, índice de Cronbach, cargas factoriales (rotación varimax). . Presenta una tabla resumen de los resultados en cargas factoriales (rotación varimax) y varianza justificada en tantos por ciento de la aplicación de cada test que se correponde al análisis de lso cuatro factores analizados. . El factor de razonamiento abstracto general se puede identificar mediante los test DOMINO D-48, DAT-AR, PMA-R1 y PMA-R3. Relaciones lógicas entre conjuntos es un factor que se puede identificar mediante los tests: TRS-L1 y el TRL-F. El TRL-L1 mide las relaciones lógicas a partir de símbolos verbales y letras. El TRL-F mide las relaciones lógicas a partir de figuras..

Per un consum racional i una utilitzaci?? intel??ligent de les pantalles

Resumen basado en el de la publicaci??n