Queuing and routing in a hierarchical powerline communication system

Although power-line communication (PLC) is not a new technology, its use to support data communication with timing requirements is still the focus of ongoing research. A new infrastructure intended for communication using power lines from a central location to dispersed nodes using inexpensive devices was presented recently. This new infrastructure uses a two-level hierarchical power-line system, together with an IP-based network. Due to the master-slave behaviour of the PLC medium access, together with the inherent dynamic topology of power-line networks, a mechanism to provide end-to-end communication through the two levels of the power-line system must be provided. In this paper we introduce the architecture of the PLC protocol layer that is being implemented for this end.

The generalized multiprocessor periodic resource interface model for hierarchical multiprocessor scheduling

Composition is a practice of key importance in software engineering. When real-time applications are composed it is necessary that their timing properties (such as meeting the deadlines) are guaranteed. The composition is performed by establishing an interface between the application and the physical platform. Such an interface does typically contain information about the amount of computing capacity needed by the application. In multiprocessor platforms, the interface should also present information about the degree of parallelism. Recently there have been quite a few interface proposals. However, they are either too complex to be handled or too pessimistic.In this paper we propose the Generalized Multiprocessor Periodic Resource model (GMPR) that is strictly superior to the MPR model without requiring a too detailed description. We describe a method to generate the interface from the application specification. All these methods have been implemented in Matlab routines that are publicly available.

Software transactional memory as a building block for parallel embedded realtime systems

The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

A preliminary idea for an 8-competitive, log2 DMAX + log2 log2 1/U asymptotic-space, interface generation algorithm for two-level hierarchical scheduling of constrained-deadline sporadic tasks on a uniprocessor

Consider a single processor and a software system. The software system comprises components and interfaces where each component has an associated interface and each component comprises a set of constrained-deadline sporadic tasks. A scheduling algorithm (called global scheduler) determines at each instant which component is active. The active component uses another scheduling algorithm (called local scheduler) to determine which task is selected for execution on the processor. The interface of a component makes certain information about a component visible to other components; the interfaces of all components are used for schedulability analysis. We address the problem of generating an interface for a component based on the tasks inside the component. We desire to (i) incur only a small loss in schedulability analysis due to the interface and (ii) ensure that the amount of space (counted in bits) of the interface is small; this is because such an interface hides as much details of the component as possible. We present an algorithm for generating such an interface.

WCET analysis considering contention on memory bus in COTS-based multicores

The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).

Managing contention of software transactional memory in real-time systems

The foreseen evolution of chip architectures to higher number of, heterogeneous, cores, with non-uniform memory and non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as an alternative to lock-based synchronisation. However, STM relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upperbounded and task sets can be feasibly scheduled. In this paper we defend the role of the transaction contention manager to reduce the number of transaction retries and to help the real-time scheduler assuring schedulability. For such purpose, the contention management policy should be aware of on-line scheduling information.

In-situ X-ray diffraction studies during growth of Ni-Ti shape memory alloy films and their complementary ex-situ characterization

Shape Memory Alloy (SMA) Ni-Ti films have attracted much interest as functional and smart materials due to their unique properties. However, there are still important issues unresolved like formation of film texture and its control as well as substrate effects. Thus, the main challenge is not only the control of the microstructure, including stoichiometry and precipitates, but also the identification and control of the preferential orientation since it is a crucial factor in determining the shape memory behaviour. The aim of this PhD thesis is to study the optimisation of the deposition conditions of films of Ni-Ti in order to obtain the material fully crystallized at the end of the deposition, and to establish a clear relationship between the substrates and texture development. In order to achieve this objective, a two-magnetron sputter deposition chamber has been used allowing to heat and to apply a bias voltage to the substrate. It can be mounted into the six-circle diffractometer of the Rossendorf Beamline (ROBL) at the European Synchrotron Radiation Facility (ESRF), Grenoble, France, enabling an in-situ characterization by X-ray diffraction(XRD) of the films during their growth and annealing. The in-situ studies enable us to identify the different steps of the structural evolution during deposition with a set of parameters as well as to evaluate the effect of changing parameters on the structural characteristics of the deposited film. Besides the in-situ studies, other complementary ex-situ characterization techniques such as XRD at a laboratory source, Rutherford backscattering spectroscopy(RBS), Auger electron spectroscopy (AES), cross-sectional transmission electron microscopy (X-TEM), scanning electron microscopy (SEM), and electrical resistivity (ER) measurements during temperature cycling have been used for a fine structural characterization. In this study, mainly naturally and thermally oxidized Si(100) substrates, TiN buffer layers with different thicknesses (i.e. the TiN topmost layer crystallographic orientation is thickness dependent) and MgO(100) single crystals were used as substrates. The chosen experimental procedure led to a controlled composition and preferential orientation of the films. The type of substrate plays an important role for the texture of the sputtered Ni-Ti films and according to the ER results, the distinct crystallographic orientations of the Ni-Ti films influence their phase transformation characteristics.

Effects of oxidante acid treatments on carbon-templated hierarchical SAPO-11 materials: synthesis, characterization and catalytic evaluation in n-decane hydroiosomerization

Hierarchical SAPO-11 was synthesized using a commercial Merck carbon as template. Oxidant acid treatments were performed on the carbon matrix in order to investigate its influence on the properties of SAPO-11. Structural, textural and acidic properties of the different materials were evaluated by XRD, SEM, N-2 adsorption, pyridine adsorption followed by IR spectroscopy and thermal analyses. The catalytic behavior of the materials (with 0.5 wt.% Pt, introduced by mechanic mixture with Pt/Al2O3), were studied in the hydroisomerization of n-decane. The hierarchical samples showed higher yields in monobranched isomers than typical microporous SAPO-11, as a direct consequence of the modification on both porosity and acidity, the later one being the most predominant. (C) 2014 Elsevier B.V. All rights reserved.

Consistent state software transactional memory

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do Grau de Mestre em Engenharia Informática

Hierarchical wrinkling on elastometric Janus spheres

Hierarchical wrinkling on elastomeric Janus spheres is permanently imprinted by swelling, for different lengths of time, followed by drying the particles in an appropriate solvent. First-order buckling with a spatial periodicity (lambda(11)) of the order of a few microns and hierarchical structures comprising of 2nd order buckling with a spatial periodicity (lambda(12)) of the order of hundreds of nanometers have been obtained. The 2nd order buckling features result from a Grinfeld surface instability due to the diffusion of the solvent and the presence of sol molecules.

Speculative execution by using software transactional memory

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do Grau de Mestre em Engenharia Informática.

Write-erase and read paper memory transistor

Applied Physics Letters, Vol.93, issue 20

The impact of the 2008 and 2010 financial crises on international stock markets : contagion and long memory

Nesta tese estudamos os efeitos de contágio financeiro e de memória longa causados pelas crises financeiras de 2008 e 2010 em alguns mercados acionistas internacionais. A tese é composta por três ensaios interligados. No Ensaio 1, recorremos à teoria das cópulas para testar a existência de contágio e revelar os canais “investor induced” de transmissão da crise de 2008 aos mercados da Bélgica, França, Holanda e Portugal (grupo NYSE Euronext). Concluímos que existe contágio nestes mercados, que o canal “portfolio rebalancing” é o mecanismo mais importante de transmissão da crise, e que o fenómeno “flight to quality” está presente nos mercados. No Ensaio 2, usando novamente modelos de cópulas, avaliamos os efeitos de contágio provocados pelo mercado acionista grego nos mercados do grupo NYSE Euronext, no contexto da crise de 2010. Os resultados obtidos sugerem que durante a crise de 2010 apenas o mercado português foi objeto de contágio; além disso, conclui-se que os efeitos de contágio provocados pela crise de 2008 são claramente superiores aos efeitos provocados pela crise de 2010. No Ensaio 3, abordamos o tema da memória longa através do estudo do expoente de Hurst dos mercados acionistas da Bélgica, E.U.A., França, Grécia, Holanda, Japão, Reino Unido e Portugal. Verificamos que as propriedades de memória longa dos mercados foram afetadas pelas crises, especialmente a de 2008 – que aumentou a memória longa dos mercados e tornou-os mais persistentes. Finalmente, usando cópulas mais uma vez, verificamos que as crises provocaram, em geral, um aumento na correlação entre os expoentes de Hurst locais dos mercados foco das crises (E.U.A. e Grécia) e os expoentes de Hurst locais dos outros mercados da amostra, sugerindo que o expoente de Hurst pode ser utilizado para detetar efeitos de contágio financeiro. Em síntese, os resultados desta tese sugerem que comparativamente com períodos de acalmia, os períodos de crises financeiras tendem a provocar ineficiência nos mercados acionistas e a conduzi-los na direção da persistência e do contágio financeiro.