A DC-DC Step-Up mu-Power Converter for Energy Harvesting Applications, Using Maximum Power PointTracking, Based on Fractional Open Circuit Voltage

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

Equivalent Circuits and Nanoplasmonics

We show how a circuit analysis, used widely in electrical engineering, finds application to problems of light wave injection and transport in subwavelength structures in the optical frequency range. Lumped circuit and transmission-line analysis may prove helpful in the design of plasmonic devices with standard, functional properties.

Electrothermal characterization and nonlinear modelling of GaN transistors for telecommunication circuit design

This thesis starts showing the main characteristics and application fields of the AlGaN/GaN HEMT technology, focusing on reliability aspects essentially due to the presence of low frequency dispersive phenomena which limit in several ways the microwave performance of this kind of devices. Based on an equivalent voltage approach, a new low frequency device model is presented where the dynamic nonlinearity of the trapping effect is taken into account for the first time allowing considerable improvements in the prediction of very important quantities for the design of power amplifier such as power added efficiency, dissipated power and internal device temperature. An innovative and low-cost measurement setup for the characterization of the device under low-frequency large-amplitude sinusoidal excitation is also presented. This setup allows the identification of the new low frequency model through suitable procedures explained in detail. In this thesis a new non-invasive empirical method for compact electrothermal modeling and thermal resistance extraction is also described. The new contribution of the proposed approach concerns the non linear dependence of the channel temperature on the dissipated power. This is very important for GaN devices since they are capable of operating at relatively high temperatures with high power densities and the dependence of the thermal resistance on the temperature is quite relevant. Finally a novel method for the device thermal simulation is investigated: based on the analytical solution of the tree-dimensional heat equation, a Visual Basic program has been developed to estimate, in real time, the temperature distribution on the hottest surface of planar multilayer structures. The developed solver is particularly useful for peak temperature estimation at the design stage when critical decisions about circuit design and packaging have to be made. It facilitates the layout optimization and reliability improvement, allowing the correct choice of the device geometry and configuration to achieve the best possible thermal performance.

Influence of the magnesium aspartate hydrochloride administration to the maternal circuit on the aspartate concentration of the fetal circuit under in vitro perfusion of human placenta

OBJECTIVES: Magnesium aspartate hydrochloride (Magnesiocard, Mg-Asp-HCl) is proposed as a substitute of magnesium sulfate for the treatment of preeclampsia and premature labor. After an i.v. administration of a dose equivalent to that used in the treatment of preeclampsia to nonpregnant volunteers, a 10-fold increase of aspartic acid (Asp) over the physiological level was observed. Animal experiments have demonstrated that highly increased fetal levels of acidic amino acids such as Asp could be associated with neurotoxic damage in the fetal brain. The influence of such an elevation of Asp concentration in the maternal circuit on the fetal level, using the in vitro perfusion model of human placenta, was investigated. STUDY DESIGN: After a control phase (2h), a therapeutic dose of Mg combined with Asp (Magnesiocard, Mg-Asp-HCl) was applied to the maternal circuit approaching 10 times the physiological level of Asp. The administration was performed in two different phases simulating either a peak of maximum concentration (bolus application, 2h) or a steady state level (initially added, 4h). RESULTS: In four experiments, during experimental phases (6h) a slow increase in concentration in the fetal circuit was seen for Mg, AIB (alpha-aminoisobutyric acid, artificial amino acid) and creatinine confirming previous observations. In contrast, no net transfer of Asp across the placenta was seen. A continuous decrease in the concentration of Asp on both maternal and fetal side suggests active uptake and metabolization by the placenta. Viability control parameters remained stable indicating the absence of an effect on placental metabolism, permeability and morphology. CONCLUSION: Elevation of Asp concentration up to 10 times the physiological level by the administration of Mg-Asp-HCl to the maternal circuit under in vitro perfusion conditions of human placenta has no influence on the fetal level of Asp suggesting no transfer of Asp from the maternal to fetal compartment. Therefore, the administration of Mg-Asp-HCl to preeclamptic patients would be beneficial for the patients without any impact on placental or fetal physiology.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

A geometric approach to quantum circuit lower bounds

What is the minimal size quantum circuit required to exactly implement a specified n-qubit unitary operation, U, without the use of ancilla qubits? We show that a lower bound on the minimal size is provided by the length of the minimal geodesic between U and the identity, I, where length is defined by a suitable Finsler metric on the manifold SU(2(n)). The geodesic curves on these manifolds have the striking property that once an initial position and velocity are set, the remainder of the geodesic is completely determined by a second order differential equation known as the geodesic equation. This is in contrast with the usual case in circuit design, either classical or quantum, where being given part of an optimal circuit does not obviously assist in the design of the rest of the circuit. Geodesic analysis thus offers a potentially powerful approach to the problem of proving quantum circuit lower bounds. In this paper we construct several Finsler metrics whose minimal length geodesics provide lower bounds on quantum circuit size. For each Finsler metric we give a procedure to compute the corresponding geodesic equation. We also construct a large class of solutions to the geodesic equation, which we call Pauli geodesics, since they arise from isometries generated by the Pauli group. For any unitary U diagonal in the computational basis, we show that: (a) provided the minimal length geodesic is unique, it must be a Pauli geodesic; (b) finding the length of the minimal Pauli geodesic passing from I to U is equivalent to solving an exponential size instance of the closest vector in a lattice problem (CVP); and (c) all but a doubly exponentially small fraction of such unitaries have minimal Pauli geodesics of exponential length.

Effect Of Pain Chronification And Chronic Pain On An Endogenous Pain Modulation Circuit In Rats.

We tested the hypothesis that chronic pain development (pain chronification) and ongoing chronic pain (chronic pain) reduce the activity and induce plastic changes in an endogenous analgesia circuit, the ascending nociceptive control. An important mechanism mediating this form of endogenous analgesia, referred to as capsaicin-induced analgesia, is its dependence on nucleus accumbens μ-opioid receptor mechanisms. Therefore, we also investigated whether pain chronification and chronic pain alter the requirement for nucleus accumbens μ-opioid receptor mechanisms in capsaicin-induced analgesia. We used an animal model of pain chronification in which daily subcutaneous prostaglandin E2 (PGE2) injections into the rat's hind paw for 14 days, referred to as the induction period of persistent hyperalgesia, induce a long-lasting state of nociceptor sensitization referred to as the maintenance period of persistent hyperalgesia, that lasts for at least 30 days following the cessation of the PGE2 treatment. The nociceptor hypersensitivity was measured by the shortening of the time interval for the animal to respond to a mechanical stimulation of the hind paw. We found a significant reduction in the duration of capsaicin-induced analgesia during the induction and maintenance period of persistent mechanical hyperalgesia. Intra-accumbens injection of the μ-opioid receptor selective antagonist Cys(2),Tyr(3),Orn(5),Pen(7)amide (CTOP) 10 min before the subcutaneous injection of capsaicin into the rat's fore paw blocked capsaicin-induced analgesia. Taken together, these findings indicate that pain chronification and chronic pain reduce the duration of capsaicin-induced analgesia, without affecting its dependence on nucleus accumbens μ-opioid receptor mechanisms. The attenuation of endogenous analgesia during pain chronification and chronic pain suggests that endogenous pain circuits play an important role in the development and maintenance of chronic pain.

Creatina quinase e dor muscular tardia na musculação : estudo experimental em adultos e jovens com o "circuit weight training" e o "multiple set system"

Universidade Estadual de Campinas . Faculdade de Educação Física

Per capita versus adult-equivalent estimates of calorie availability in household budget surveys

This study aims to estimate an adult-equivalent scale for calorie requirements and to determine the differences between adult-equivalent and per capita measurements of calorie availability in the Brazilian population. The study used data from the 2002-2003 Brazilian Household Budget Survey. The calorie requirement for a reference adult individual was based on the mean requirements for adult males and females (2,550kcal/day). The conversion factors were defined as the ratios between the calorie requirements for each age group and gender and that of the reference adult. The adult-equivalent calorie availability levels were higher than the per capita levels, with the largest differences in rural and low-income households. Differences in household calorie availability varied from 22kcal/day (households with adults and an adolescent) to 428kcal/day (households with elderly individuals), thus showing that per capital measurements can underestimate the real calorie availability, since they overlook differences in household composition.

Autocatalysis in the open circuit interaction of alcohol molecules with oxidized Pt surfaces

We studied the open circuit interaction of methanol and ethanol with oxidized platinum electrodes using in situ infrared spectroscopy. For methanol, it was found that formic acid is the main species formed in the initial region of the transient and that the steep decrease of the open circuit potential coincides with an explosive increase in the CO(2) production, which is followed by an increase in the coverage of adsorbed CO. For ethanol, acetaldehyde was the main product detected and only traces of dissolved CO(2) and adsorbed CO were found after the steep potential decay. In both cases, the transients were interpreted in terms of (a) the emergence of sub-surface oxygen in the beginning of the transient, where the oxide content is high, and (b) the autocatalytic production of free platinum sites for lower oxide content during the steep decay of the open circuit potential.

Acute physiological responses to different circuit training protocols

Aim. The purpose of present study was to compare the acute physiological responses to a circuit weight training with the responses to a combined circuit training (weight training and treadmill run). Methods. The sample consisted of 25 individuals at an average state of training, 10 men and 15 female, between 18 and 35 year old. There were selected 60 second sets of resistance exercises to the circuit weight training (CWT). Whereas in the combined circuit training (CCT), the subjects spent 30 seconds on the same resistance exercises and 30 seconds running on the treadmill. The rest intervals between the sets lasted 15 seconds. The analysis of variance (ANOVA) with 5% significance level was utilized to the statistical analysis of the results. Results. Comparing circuit training protocols, it was noted that CCT elicits a higher relative and absolute <(V)over dot>O(2) and energy expenditure values than CWT for both genders (P<0.05). Regarding inter-gender comparison, males showed higher absolute and relative <(V)over dot>O(2) and absolute energy expenditure values for both CWT and CCT than females (P<0.05). Females showed a significant greater % <(V)over dot>O(2max) value for both CWT and CCT. Due to the experimental conditions used to state both circuit training bouts (CWT and CCT), the <(V)over dot>O(2) rate found was higher than the values reported by previous studies which used heavier weight lift. Conclusion. CCT seems adequate to produce cardiovascular improvements and greater energy expenditure for both men and women, while CWT group classes are sufficient only for unfit women.

Chaotic communication based on the particle-in-a-box electronic circuit

A secure communication system based on the error-feedback synchronization of the electronic model of the particle-in-a-box system is proposed. This circuit allows a robust and simple electronic emulation of the mechanical behavior of the collisions of a particle inside a box, exhibiting rich chaotic behavior. The required nonlinearity to emulate the box walls is implemented in a simple way when compared with other analog electronic chaotic circuits. A master/slave synchronization of two circuits exhibiting a rich chaotic behavior demonstrates the potentiality of this system to secure communication. In this system, binary data stream information modulates the bifurcation parameter of the particle-in-a-box electronic circuit in the transmitter. In the receiver circuit, this parameter is estimated using Pecora-Carroll synchronization and error-feedback synchronization. The performance of the demodulation process is verified through the eye pattern technique applied on the recovered bit stream. During the demodulation process, the error-feedback synchronization presented better performance compared with the Pecora-Carroll synchronization. The application of the particle-in-a-box electronic circuit in a secure communication system is demonstrated.

Hyperchaos in a Chua`s circuit with two new added branches

In this work a fourth-order Chua`s circuit, capable of generating hyperchaotic oscillations in a wide range of parameters, is presented. The circuit is obtained by adding two new branches to the original topology of the Chua`s double scroll circuit. One of the added branches is a linear inductor-resistor series connection, and the other one is a nonlinear voltage-controlled current source. A theoretical analysis of the circuit equations is presented, along with numerical and experimental results.

The four-element Chua`s circuit

A new circuit configuration, linearly conjugate to the standard Chua`s circuit, is presented. Its distinctive feature is that the equations now admit an additional parameter, which controls the dissipation in the network connected to the Chua diode. In the limiting case we obtain the simplest chaotic circuit, consisting of a piecewise-linear resistor and three lossless elements.

Modeling and analysis of laminate composite plates with embedded active-passive piezoelectric networks

The objective of this work is to present the finite element modeling of laminate composite plates with embedded piezoelectric patches or layers that are then connected to active-passive resonant shunt circuits, composed of resistance, inductance and voltage source. Applications to passive vibration control and active control authority enhancement are also presented and discussed. The finite element model is based on an equivalent single layer theory combined with a third-order shear deformation theory. A stress-voltage electromechanical model is considered for the piezoelectric materials fully coupled to the electrical circuits. To this end, the electrical circuit equations are also included in the variational formulation. Hence, conservation of charge and full electromechanical coupling are guaranteed. The formulation results in a coupled finite element model with mechanical (displacements) and electrical (charges at electrodes) degrees of freedom. For a Graphite-Epoxy (Carbon-Fibre Reinforced) laminate composite plate, a parametric analysis is performed to evaluate optimal locations along the plate plane (xy) and thickness (z) that maximize the effective modal electromechanical coupling coefficient. Then, the passive vibration control performance is evaluated for a network of optimally located shunted piezoelectric patches embedded in the plate, through the design of resistance and inductance values of each circuit, to reduce the vibration amplitude of the first four vibration modes. A vibration amplitude reduction of at least 10 dB for all vibration modes was observed. Then, an analysis of the control authority enhancement due to the resonant shunt circuit, when the piezoelectric patches are used as actuators, is performed. It is shown that the control authority can indeed be improved near a selected resonance even with multiple pairs of piezoelectric patches and active-passive circuits acting simultaneously. (C) 2010 Elsevier Ltd. All rights reserved.