Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Simple equidistant firing delay scheme for 3-phi thyristor converters

A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

Voltage delay during constant-current or constant-resistance discharge of Mg-MnO2 dry cells: A comparative study

A theoretical approach has been developed to relate the voltage delay transients of the Mg-MnO2 dry cell observed during discharge by two commonly employed modes, viz., (1) at constant current, and (2) across a constant resistance. The approach has been verified by comparison of experimentally obtained transients with those generated from theory. The method may be used to predict the delay parameters of the Mg-MnO2 dry cell under the two modes of discharge and can, in principle, be extended to lithium batteries.

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7 x 10(-6) K-1 (25 degrees C-100 degrees C) and a thermal conductivity of 147 Wm(-1) K-1 at 30 degrees C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100 degrees C-400 degrees C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30 degrees C to 400 degrees C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

A Reactive Tabu Search Based Equalizer for Severely Delay-Spread UWB MIMO-ISI Channels

We propose a novel equalizer for ultrawideband (UWB) multiple-input multiple-output (MIMO) channels characterized by severe delay spreads. The proposed equalizer is based on reactive tabu search (RTS), which is a heuristic originally designed to obtain approximate solutions to combinatorial optimization problems. The proposed RTS equalizer is shown to perform increasingly better for increasing number of multipath components (MPC), and achieve near maximum likelihood (ML) performance for large number of MPCs at a much less complexity than that of the ML detector. The proposed RTS equalizer is shown to perform close to within 0.4 dB of single-input multiple-output AWGN performance at 10(-3) uncoded BER on a severely delay-spread UWB MIMO channel with 48 equal-energy MPCs.

The non-linear response of a gyrostabilized platform: Effects of correction torque time delay and of random inputs

First, the non-linear response of a gyrostabilized platform to a small constant input torque is analyzed in respect to the effect of the time delay (inherent or deliberately introduced) in the correction torque supplied by the servomotor, which itself may be non-linear to a certain extent. The equation of motion of the platform system is a third order nonlinear non-homogeneous differential equation. An approximate analytical method of solution of this equation is utilized. The value of the delay at which the platform response becomes unstable has been calculated by using this approximate analytical method. The procedure is illustrated by means of a numerical example. Second, the non-linear response of the platform to a random input has been obtained. The effects of several types of non-linearity on reducing the level of the mean square response have been investigated, by applying the technique of equivalent linearization and solving the resulting integral equations by using laguerre or Gaussian integration techniques. The mean square responses to white noise and band limited white noise, for various values of the non-linear parameter and for different types of non-linearity function, have been obtained. For positive values of the non-linear parameter the levels of the non-linear mean square responses to both white noise and band-limited white noise are low as compared to the linear mean square response. For negative values of the non-linear parameter the level of the non-linear mean square response at first increases slowly with increasing values of the non-linear parameter and then suddenly jumps to a high level, at a certain value of the non-linearity parameter.

An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning

In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect-networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as correlated Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Function (PDF) at all nodes in the interconnect network. Main objective is to find delay PDF at a cheaper cost. Convergence of this approach is in probability distribution but not in mean of delay. We validate our approach against SPICE based Monte Carlo simulations while the current method entails significantly lower computational cost.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Effect of tolerance on the propagation characteristic of a superconducting thin film microstrip delay line

The propagation constant of a superconducting microstrip transmission delay line is evaluated using the spectral domain immitance approach, modelling the superconductor as a surface current having an equivalent surface impedance found through the complex resistive boundary condition. The sensitivity approach is used to study the beta variations with substrate parameters and film characteristics. Results show that the surface impedance does not have much influence on beta sensitivities with respect to epsilon r, W and h. However, it can be observed that the surface impedance plays a crucial role in determining the optimum design.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Link failure detection for maintaining session continuity in packet data networks

A link failure in the path of a virtual circuit in a packet data network will lead to premature disconnection of the circuit by the end-points. A soft failure will result in degraded throughput over the virtual circuit. If these failures can be detected quickly and reliably, then appropriate rerouteing strategies can automatically reroute the virtual circuits that use the failed facility. In this paper, we develop a methodology for analysing and designing failure detection schemes for digital facilities. Based on errored second data, we develop a Markov model for the error and failure behaviour of a T1 trunk. The performance of a detection scheme is characterized by its false alarm probability and the detection delay. Using the Markov model, we analyse the performance of detection schemes that use physical layer or link layer information. The schemes basically rely upon detecting the occurrence of severely errored seconds (SESs). A failure is declared when a counter, that is driven by the occurrence of SESs, reaches a certain threshold.For hard failures, the design problem reduces to a proper choice;of the threshold at which failure is declared, and on the connection reattempt parameters of the virtual circuit end-point session recovery procedures. For soft failures, the performance of a detection scheme depends, in addition, on how long and how frequent the error bursts are in a given failure mode. We also propose and analyse a novel Level 2 detection scheme that relies only upon anomalies observable at Level 2, i.e. CRC failures and idle-fill flag errors. Our results suggest that Level 2 schemes that perform as well as Level 1 schemes are possible.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Delay constrained optimal relay placement for planned wireless sensor networks

In this paper, we study the problem of wireless sensor network design by deploying a minimum number of additional relay nodes (to minimize network design cost) at a subset of given potential relay locationsin order to convey the data from already existing sensor nodes (hereafter called source nodes) to a Base Station within a certain specified mean delay bound. We formulate this problem in two different ways, and show that the problem is NP-Hard. For a problem in which the number of existing sensor nodes and potential relay locations is n, we propose an O(n) approximation algorithm of polynomial time complexity. Results show that the algorithm performs efficiently (in over 90% of the tested scenarios, it gave solutions that were either optimal or exceeding optimal just by one relay) in various randomly generated network scenarios.