Pantalla táctil para el piloto en un monoplaza de la fórmula SAE

En este proyecto se ha desarrollado un sistema electrónico para un vehículo de Fórmula SAE. La Fórmula SAE es una competición orientada a estudiantes que se basa en el diseño y fabricación de un vehículo de carreras. Este vehículo será posteriormente testeado en una competición a nivel mundial. El principal objetivo de este proyecto es el estudio, diseño y creación de un sistema para la visualización de información en un vehículo a través de una pantalla táctil. El núcleo del sistema será un microcontrolador de 32 bits de Microchip programado en C sobre un sistema de desarrollo integrado. El sistema mostrará información que pueda ser de utilidad para el piloto del coche. La información que se mostrará en la pantalla provendrá de los diferentes sensores del propio vehículo (velocidad, rpm, temperatura, estado de la batería). Dichos sensores se comunicarán con el sistema a través de comunicación CAN Bus. Para el testeo del sistema se utilizará una herramienta de simulación CAN. Además de mostrar información, el piloto será capaz de seleccionar entre diferentes configuraciones para la conducción desde el propio volante. El sistema contiene además los elementos necesarios para la programación y depuración del microcontrolador PIC. ABSTRACT. In this project, an electronic application for a Formula SAE vehicle has been developed. The Formula SAE is a student-oriented competition based on the design and manufacture of a race car. This car will be later tested in a worldwide competition. The principal aim of this project is the study, design and manufacture of a system for the display of a vehicle’s information through a touch screen. The system core will be a 32-bit Microchip microcontroller programmed in C code over an Integrated Development Environment. The system will display useful information to the car driver. The information shown on the screen will come from the different sensors of the vehicle itself (speed, rpm, temperature, battery status). Those sensors will communicate with the system via CAN Bus. A CAN Bus simulator device will be used during the design testing. In addition to displaying information, the pilot will be able to select different driving configurations from the steering wheel itself. The system also contains the necessary elements for programming and debugging the PIC microcontroller.

Desarrollo de un proceso de normalización semántica de bases de datos en ensayos clínicos

El trabajo se enmarca dentro de los proyecto INTEGRATE y EURECA, cuyo objetivo es el desarrollo de una capa de interoperabilidad semántica que permita la integración de datos e investigación clínica, proporcionando una plataforma común que pueda ser integrada en diferentes instituciones clínicas y que facilite el intercambio de información entre las mismas. De esta manera se promueve la mejora de la práctica clínica a través de la cooperación entre instituciones de investigación con objetivos comunes. En los proyectos se hace uso de estándares y vocabularios clínicos ya existentes, como pueden ser HL7 o SNOMED, adaptándolos a las necesidades particulares de los datos con los que se trabaja en INTEGRATE y EURECA. Los datos clínicos se representan de manera que cada concepto utilizado sea único, evitando ambigüedades y apoyando la idea de plataforma común. El alumno ha formado parte de un equipo de trabajo perteneciente al Grupo de Informática de la UPM, que a su vez trabaja como uno de los socios de los proyectos europeos nombrados anteriormente. La herramienta desarrollada, tiene como objetivo realizar tareas de homogenización de la información almacenada en las bases de datos de los proyectos haciendo uso de los mecanismos de normalización proporcionados por el vocabulario médico SNOMED-CT. Las bases de datos normalizadas serán las utilizadas para llevar a cabo consultas por medio de servicios proporcionados en la capa de interoperabilidad, ya que contendrán información más precisa y completa que las bases de datos sin normalizar. El trabajo ha sido realizado entre el día 12 de Septiembre del año 2014, donde comienza la etapa de formación y recopilación de información, y el día 5 de Enero del año 2015, en el cuál se termina la redacción de la memoria. El ciclo de vida utilizado ha sido el de desarrollo en cascada, en el que las tareas no comienzan hasta que la etapa inmediatamente anterior haya sido finalizada y validada. Sin embargo, no todas las tareas han seguido este modelo, ya que la realización de la memoria del trabajo se ha llevado a cabo de manera paralela con el resto de tareas. El número total de horas dedicadas al Trabajo de Fin de Grado es 324. Las tareas realizadas y el tiempo de dedicación de cada una de ellas se detallan a continuación:  Formación. Etapa de recopilación de información necesaria para implementar la herramienta y estudio de la misma [30 horas.  Especificación de requisitos. Se documentan los diferentes requisitos que ha de cumplir la herramienta [20 horas].  Diseño. En esta etapa se toman las decisiones de diseño de la herramienta [35 horas].  Implementación. Desarrollo del código de la herramienta [80 horas].  Pruebas. Etapa de validación de la herramienta, tanto de manera independiente como integrada en los proyectos INTEGRATE y EURECA [70 horas].  Depuración. Corrección de errores e introducción de mejoras de la herramienta [45 horas].  Realización de la memoria. Redacción de la memoria final del trabajo [44 horas].---ABSTRACT---This project belongs to the semantic interoperability layer developed in the European projects INTEGRATE and EURECA, which aims to provide a platform to promote interchange of medical information from clinical trials to clinical institutions. Thus, research institutions may cooperate to enhance clinical practice. Different health standards and clinical terminologies has been used in both INTEGRATE and EURECA projects, e.g. HL7 or SNOMED-CT. These tools have been adapted to the projects data requirements. Clinical data are represented by unique concepts, avoiding ambiguity problems. The student has been working in the Biomedical Informatics Group from UPM, partner of the INTEGRATE and EURECA projects. The tool developed aims to perform homogenization tasks over information stored in databases of the project, through normalized representation provided by the SNOMED-CT terminology. The data query is executed against the normalized version of the databases, since the information retrieved will be more informative than non-normalized databases. The project has been performed from September 12th of 2014, when initiation stage began, to January 5th of 2015, when the final report was finished. The waterfall model for software development was followed during the working process. Therefore, a phase may not start before the previous one finishes and has been validated, except from the final report redaction, which has been carried out in parallel with the others phases. The tasks that have been developed and time for each one are detailed as follows:  Training. Gathering the necessary information to develop the tool [30 hours].  Software requirement specification. Requirements the tool must accomplish [20 hours].  Design. Decisions on the design of the tool [35 hours].  Implementation. Tool development [80 hours].  Testing. Tool evaluation within the framework of the INTEGRATE and EURECA projects [70 hours].  Debugging. Improve efficiency and correct errors [45 hours].  Documenting. Final report elaboration [44 hours].

PCCMuTe v2.2: una herramienta para medir el consumo de energía en sistemas empotrados

Este Proyecto Fin de Grado (PFG) recoge el trabajo de depuración realizado sobre el prototipo PCCMuTe v2.2, un sistema empotrado que dispone de la instrumentación necesaria para medir el consumo de potencia/energía en cada uno de sus dominios de tensión, y posteriormente digitalizar y enviar los resultados al procesador que se encuentra en su interior. Su uso permite la obtención de información en tiempo real sobre el consumo del hardware de la placa, en especial del procesador, pudiendo relacionar la potencia consumida con el software ejecutado. El proyecto está orientado a medir el consumo de energía derivado de la decodificación de vídeo. El software utilizado para controlar el hardware se basa en Linux. En este proyecto se distinguen principalmente dos actividades, depuración hardware y depuración software. Los resultados muestran avances en la depuración hardware hasta obtener un prototipo en completo funcionamiento. Los avances en el apartado del software habilitan las comunicaciones SPI, necesarias para la transmisión de los resultados de consumo al procesador. En la fase final de este PFG se hace uso de una aplicación previamente desarrollada por miembros del GDEM con la que se obtienen los primeros datos de consumo, pero por falta de tiempo estos resultados no pueden ser verificados. Por la misma razón no ha sido posible diseñar y codificar una nueva aplicación que mejore la forma en la que se obtienen esos datos. ABSTRACT. This bachelor final project includes the debugging work done on the prototype PCCMuTe v2.2, an embedded system with the necessary instrumentation to measure the power/ energy consumption in each of its voltage domains, scan and send the results to its processor. The purpose of this device is to obtain real-time information about the hardware power consumption, especially from the processor, being able to relate the power consumed with the software executed. The project aims to measure the energy consumption of video decoding. The software used to control the hardware is based on Linux. In this project there are two main activities: hardware and software debugging. The results show advances in hardware debugging, and finally a fully functioning prototype is obtained. Advances in software debugging enable SPI communications, used to transmit the consumption data to the processor. In the last part of this final bachelor project an application previously coded by other members of the GDEM is used to obtain the first data. The results can not finally be verified because of the lack of time. For the same reason it is not possible to design and code a new application that improves the way the data is obtained.

Practical domain-specific debuggers using the Moldable Debugger framework

Understanding the run-time behavior of software systems can be a challenging activity. Debuggers are an essential category of tools used for this purpose as they give developers direct access to the running systems. Nevertheless, traditional debuggers rely on generic mechanisms to introspect and interact with the running systems, while developers reason about and formulate domain-specific questions using concepts and abstractions from their application domains. This mismatch creates an abstraction gap between the debugging needs and the debugging support leading to an inefficient and error-prone debugging effort, as developers need to recover concrete domain concepts using generic mechanisms. To reduce this gap, and increase the efficiency of the debugging process, we propose a framework for developing domain-specific debuggers, called the Moldable Debugger, that enables debugging at the level of the application domain. The Moldable Debugger is adapted to a domain by creating and combining domain-specific debugging operations with domain-specific debugging views, and adapts itself to a domain by selecting, at run time, appropriate debugging operations and views. To ensure the proposed model has practical applicability (i.e., can be used in practice to build real debuggers), we discuss, from both a performance and usability point of view, three implementation strategies. We further motivate the need for domain-specific debugging, identify a set of key requirements and show how our approach improves debugging by adapting the debugger to several domains.

Sociopathic knowledge bases : correct knowledge can be harmful even given unlimited computation /

"College of Engineering, UILU-ENG-89-1757."

Syntactic error recovery for LR parsers /

Thesis (M. S.)--University of Illinois at Urbana-Champaign.

Syntax-directed error recovery for compilers /

Photocopy. Ann Arbor, Mich. : Xerox University Microfilms, 1976. -- 21 cm.

An interactive analysis system for execution-time errors /

Bibliography: p. 65-66.

A Log Tool for Software Systems Analyses

The article presents a new type of logs merging tool for multiple blade telecommunication systems based on the development of a new approach. The introduction of the new logs merging tool (the Log Merger) can help engineers to build a processes behavior timeline with a flexible system of information structuring used to assess the changes in the analyzed system. This logs merging system based on the experts experience and their analytical skills generates a knowledge base which could be advantageous in further decision-making expert system development. This paper proposes and discusses the design and implementation of the Log Merger, its architecture, multi-board analysis of capability and application areas. The paper also presents possible ways of further tool improvement e.g. - to extend its functionality and cover additional system platforms. The possibility to add an analysis module for further expert system development is also considered.

Data Mining for Software Development Life Cycle Quality Management

Computer software plays an important role in business, government, society and sciences. To solve real-world problems, it is very important to measure the quality and reliability in the software development life cycle (SDLC). Software Engineering (SE) is the computing field concerned with designing, developing, implementing, maintaining and modifying software. The present paper gives an overview of the Data Mining (DM) techniques that can be applied to various types of SE data in order to solve the challenges posed by SE tasks such as programming, bug detection, debugging and maintenance. A specific DM software is discussed, namely one of the analytical tools for analyzing data and summarizing the relationships that have been identified. The paper concludes that the proposed techniques of DM within the domain of SE could be well applied in fields such as Customer Relationship Management (CRM), eCommerce and eGovernment. ACM Computing Classification System (1998): H.2.8.

Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform

Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

Supporting Run-time Monitoring of UML-RT through Customizable Monitoring Configurations in PapyrusRT

Model Driven Engineering uses the principle that code can automatically be generated from software models which would potentially save time and cost of development. By this methodology, a systems structure and behaviour can be expressed in more abstract, high level terms without some of the accidental complexity that the use of a general purpose language can bring. Models are the actual implementation of the system unlike in traditional software development where models are often used for documentation purposes only. However once the code is generated from the model, testing and debugging activities tend to happen on the code level and the model is not updated. We believe that monitoring on the model level could potentially facilitate quality assurance activities as the errors are detected in the early phase of development. In this thesis, we create a Monitoring Configuration for an open source model driven engineering tool called PapyrusRT in Eclipse. We support the run-time monitoring of UML-RT elements with a tracing tool called LTTng. We annotate the model with monitoring information to be used by the code generator for adding tracepoint statements for the corresponding elements. We provide the option of a timing specification to discover latency errors on the model. We validate the results by creating and tracing real time models in PapyrusRT.

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.

PORBS: A parallel observation-based slicer

Abstract—This paper presents PORBS, a parallelised observation-based slicing tool. The tool itself is written in Java making it platform independent and leverages the build chain of the system being sliced to avoid the need to replicate complex compiler analysis. The target audience of PORBS is software engineers and researchers working with and on tools and techniques for software comprehension, debugging, re-engineering, and maintenance.

The Design and Implementation of a SD Card File System

SD card (Secure Digital Memory Card) is widely used in portable storage medium. Currently, latest researches on SD card, are mainly SD card controller based on FPGA (Field Programmable Gate Array). Most of them are relying on API interface (Application Programming Interface), AHB bus (Advanced High performance Bus), etc. They are dedicated to the realization of ultra high speed communication between SD card and upper systems. Studies about SD card controller, really play a vital role in the field of high speed cameras and other sub-areas of expertise. This design of FPGA-based file systems and SD2.0 IP (Intellectual Property core) does not only exhibit a nice transmission rate, but also achieve the systematic management of files, while retaining a strong portability and practicality. The file system design and implementation on a SD card covers the main three IP innovation points. First, the combination and integration of file system and SD card controller, makes the overall system highly integrated and practical. The popular SD2.0 protocol is implemented for communication channels. Pure digital logic design based on VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), integrates the SD card controller in hardware layer and the FAT32 file system for the entire system. Secondly, the document management system mechanism makes document processing more convenient and easy. Especially for small files in batch processing, it can ease the pressure of upper system to frequently access and process them, thereby enhancing the overall efficiency of systems. Finally, digital design ensures the superior performance. For transmission security, CRC (Cyclic Redundancy Check) algorithm is for data transmission protection. Design of each module is platform-independent of macro cells, and keeps a better portability. Custom integrated instructions and interfaces may facilitate easily to use. Finally, the actual test went through multi-platform method, Xilinx and Altera FPGA developing platforms. The timing simulation and debugging of each module was covered. Finally, Test results show that the designed FPGA-based file system IP on SD card can support SD card, TF card and Micro SD with 2.0 protocols, and the successful implementation of systematic management for stored files, and supports SD bus mode. Data read and write rates in Kingston class10 card is approximately 24.27MB/s and 16.94MB/s.