Efficient parallel proximity queries and an application to highly complex motion planning problems with many narrow passages

In vielen Bereichen der industriellen Fertigung, wie zum Beispiel in der Automobilindustrie, wer- den digitale Versuchsmodelle (sog. digital mock-ups) eingesetzt, um die Entwicklung komplexer Maschinen m ̈oglichst gut durch Computersysteme unterstu ̈tzen zu k ̈onnen. Hierbei spielen Be- wegungsplanungsalgorithmen eine wichtige Rolle, um zu gew ̈ahrleisten, dass diese digitalen Pro- totypen auch kollisionsfrei zusammengesetzt werden k ̈onnen. In den letzten Jahrzehnten haben sich hier sampling-basierte Verfahren besonders bew ̈ahrt. Diese erzeugen eine große Anzahl von zuf ̈alligen Lagen fu ̈r das ein-/auszubauende Objekt und verwenden einen Kollisionserken- nungsmechanismus, um die einzelnen Lagen auf Gu ̈ltigkeit zu u ̈berpru ̈fen. Daher spielt die Kollisionserkennung eine wesentliche Rolle beim Design effizienter Bewegungsplanungsalgorith- men. Eine Schwierigkeit fu ̈r diese Klasse von Planern stellen sogenannte “narrow passages” dar, schmale Passagen also, die immer dort auftreten, wo die Bewegungsfreiheit der zu planenden Objekte stark eingeschr ̈ankt ist. An solchen Stellen kann es schwierig sein, eine ausreichende Anzahl von kollisionsfreien Samples zu finden. Es ist dann m ̈oglicherweise n ̈otig, ausgeklu ̈geltere Techniken einzusetzen, um eine gute Performance der Algorithmen zu erreichen.rnDie vorliegende Arbeit gliedert sich in zwei Teile: Im ersten Teil untersuchen wir parallele Kollisionserkennungsalgorithmen. Da wir auf eine Anwendung bei sampling-basierten Bewe- gungsplanern abzielen, w ̈ahlen wir hier eine Problemstellung, bei der wir stets die selben zwei Objekte, aber in einer großen Anzahl von unterschiedlichen Lagen auf Kollision testen. Wir im- plementieren und vergleichen verschiedene Verfahren, die auf Hu ̈llk ̈operhierarchien (BVHs) und hierarchische Grids als Beschleunigungsstrukturen zuru ̈ckgreifen. Alle beschriebenen Verfahren wurden auf mehreren CPU-Kernen parallelisiert. Daru ̈ber hinaus vergleichen wir verschiedene CUDA Kernels zur Durchfu ̈hrung BVH-basierter Kollisionstests auf der GPU. Neben einer un- terschiedlichen Verteilung der Arbeit auf die parallelen GPU Threads untersuchen wir hier die Auswirkung verschiedener Speicherzugriffsmuster auf die Performance der resultierenden Algo- rithmen. Weiter stellen wir eine Reihe von approximativen Kollisionstests vor, die auf den beschriebenen Verfahren basieren. Wenn eine geringere Genauigkeit der Tests tolerierbar ist, kann so eine weitere Verbesserung der Performance erzielt werden.rnIm zweiten Teil der Arbeit beschreiben wir einen von uns entworfenen parallelen, sampling- basierten Bewegungsplaner zur Behandlung hochkomplexer Probleme mit mehreren “narrow passages”. Das Verfahren arbeitet in zwei Phasen. Die grundlegende Idee ist hierbei, in der er- sten Planungsphase konzeptionell kleinere Fehler zuzulassen, um die Planungseffizienz zu erh ̈ohen und den resultierenden Pfad dann in einer zweiten Phase zu reparieren. Der hierzu in Phase I eingesetzte Planer basiert auf sogenannten Expansive Space Trees. Zus ̈atzlich haben wir den Planer mit einer Freidru ̈ckoperation ausgestattet, die es erlaubt, kleinere Kollisionen aufzul ̈osen und so die Effizienz in Bereichen mit eingeschr ̈ankter Bewegungsfreiheit zu erh ̈ohen. Optional erlaubt unsere Implementierung den Einsatz von approximativen Kollisionstests. Dies setzt die Genauigkeit der ersten Planungsphase weiter herab, fu ̈hrt aber auch zu einer weiteren Perfor- mancesteigerung. Die aus Phase I resultierenden Bewegungspfade sind dann unter Umst ̈anden nicht komplett kollisionsfrei. Um diese Pfade zu reparieren, haben wir einen neuartigen Pla- nungsalgorithmus entworfen, der lokal beschr ̈ankt auf eine kleine Umgebung um den bestehenden Pfad einen neuen, kollisionsfreien Bewegungspfad plant.rnWir haben den beschriebenen Algorithmus mit einer Klasse von neuen, schwierigen Metall- Puzzlen getestet, die zum Teil mehrere “narrow passages” aufweisen. Unseres Wissens nach ist eine Sammlung vergleichbar komplexer Benchmarks nicht ̈offentlich zug ̈anglich und wir fan- den auch keine Beschreibung von vergleichbar komplexen Benchmarks in der Motion-Planning Literatur.

Curve Decomposition for Large Deflection Analysis of Fixed-Guided Beams With Application to Statically Balanced Compliant Mechanisms

Statically balanced compliant mechanisms require no holding force throughout their range of motion while maintaining the advantages of compliant mechanisms. In this paper, a postbuckled fixed-guided beam is proposed to provide the negative stiffness to balance the positive stiffness of a compliant mechanism. To that end, a curve decomposition modeling method is presented to simplify the large deflection analysis. The modeling method facilitates parametric design insight and elucidates key points on the force-deflection curve. Experimental results validate the analysis. Furthermore, static balancing with fixed-guided beams is demonstrated for a rectilinear proof-of-concept prototype.

A Kinetostatic Formulation for Load-Flow Visualization in Compliant Mechanisms

Load flow visualization, which is an important step in structural and machine assembly design may aid in the analysis and eventual synthesis of compliant mechanisms. In this paper, we present a kineto-static formulation to visualize load flow in compliant mechanisms. This formulation uses the concept of transferred forces to quantify load flow from input to the output of a compliant mechanism. The magnitude and direction of load flow in the constituent members enables functional decomposition of the compliant mechanism into (i) Constraints (C): members that are constrained to deform in a particular direction and (ii) Transmitters (T): members that transmit load to the output. Furthermore, it is shown that a constraint member and an adjacent transmitter member can be grouped together to constitute a fundamental building block known as an CT set whose load flow behavior is maximally decoupled from the rest of the mechanism. We can thereby explain the deformation behavior of a number of compliant mechanisms from literature by visualizing load flow, and identifying building blocks.

A Metric to Evaluate and Synthesize Distributed Compliant Mechanisms

Compliant mechanisms with evenly distributed stresses have better load-bearing ability and larger range of motion than mechanisms with compliance and stresses lumped at flexural hinges. In this paper, we present a metric to quantify how uniformly the strain energy of deformation and thus the stresses are distributed throughout the mechanism topology. The resulting metric is used to optimize cross-sections of conceptual compliant topologies leading to designs with maximal stress distribution. This optimization framework is demonstrated for both single-port mechanisms and single-input single-output mechanisms. It is observed that the optimized designs have lower stresses than their nonoptimized counterparts, which implies an ability for single-port mechanisms to store larger strain energy, and single-input single-output mechanisms to perform larger output work before failure.

Histamine increases sphingosine kinase-1 expression and activity in the human arterial endothelial cell line EA.hy 926 by a PKC-alpha-dependent mechanism

Sphingosine 1-phosphate (S1P) is a potent mitogenic signal generated from sphingosine by the action of sphingosine kinases (SKs). In this study, we show that in the human arterial endothelial cell line EA.hy 926 histamine induces a time-dependent upregulation of the SK-1 mRNA and protein expression which is followed by increased SK-1 activity. A similar upregulation of SK-1 is also observed with the direct protein kinase C activator 12-O-tetradecanoylphorbol-13-acetate (TPA). In contrast, SK-2 activity is not affected by neither histamine nor TPA. The increased SK-1 protein expression is due to stimulated de novo synthesis since cycloheximide inhibited the delayed SK-1 protein upregulation. Moreover, the increased SK-1 mRNA expression results from an increased promoter activation by histamine and TPA. In mechanistic terms, the transcriptional upregulation of SK-1 is dependent on PKC and the extracellular signal-regulated protein kinase (ERK) cascade since staurosporine and the MEK inhibitor U0126 abolish the TPA-induced SK-1 induction. Furthermore, the histamine effect is abolished by the H1-receptor antagonist diphenhydramine, but not by the H2-receptor antagonist cimetidine. Parallel to the induction of SK-1, histamine and TPA stimulate an increased migration of endothelial cells, which is prevented by depletion of the SK-1 by small interfering RNA (siRNA). To appoint this specific cell response to a specific PKC isoenzyme, siRNA of PKC-alpha, -delta, and -epsilon were used to selectively downregulate the respective isoforms. Interestingly, only depletion of PKC-alpha leads to a complete loss of TPA- and histamine-triggered SK-1 induction and cell migration. In summary, these data show that PKC-alpha activation in endothelial cells by histamine-activated H1-receptors, or by direct PKC activators leads to a sustained upregulation of the SK-1 protein expression and activity which, in turn, is critically involved in the mechanism of endothelial cell migration.

MECHANISM-BASED STRATEGIES TO ENHANCE THE ACTIONS OF A

Heat shock protein 90 (HSP90) is an abundant molecular chaperone that regulates the functional stability of client oncoproteins, such as STAT3, Raf-1 and Akt, which play a role in the survival of malignant cells. The chaperone function of HSP90 is driven by the binding and hydrolysis of ATP. The geldanamycin analog, 17-AAG, binds to the ATP pocket of HSP90 leading to the degradation of client proteins. However, treatment with 17-AAG results in the elevation of the levels of antiapoptotic proteins HSP70 and HSP27, which may lead to cell death resistance. The increase in HSP70 and HSP27 protein levels is due to the activation of the transcription factor HSF-1 binding to the promoter region of HSP70 and HSP27 genes. HSF-1 binding subsequently promotes HSP70 and HSP27 gene expression. Based on this, I hypothesized that inhibition of transcription/translation of HSP or client proteins would enhance 17-AAG-mediated cytotoxicity. Multiple myeloma (MM) cell lines MM.1S, RPMI-8226, and U266 were used as a model. To test this hypothesis, two different strategies were used. For the first approach, a transcription inhibitor was combined with 17-AAG. The established transcription inhibitor Actinomycin D (Act D), used in the clinic, intercalates into DNA and blocks RNA elongation. Stress inducible (HSP90á, HSP70 and HSP27) and constitutive (HSP90â and HSC70) mRNA and protein levels were measured using real time RT-PCR and immunoblot assays. Treatment with 0.5 µM 17-AAG for 8 hours resulted in the induction of all HSP transcript and protein levels in the MM cell lines. This induction of HSP mRNA levels was diminished by 0.05 µg/mL Act D for 12 hours in the combination treatment, except for HSP70. At the protein level, Act D abrogated the 17-AAG-mediated induction of all HSP expression levels, including HSP70. Cytotoxic evaluation (Annexin V/7-AAD assay) of Act D in combination with 17-AAG suggested additive or more than additive interactions. For the second strategy, an agent that affected bioenergy production in addition to targeting transcription and translation was used. Since ATP is necessary for the proper folding and maturation of client proteins by HSP90, ATP depletion should lead to a decrease in client protein levels. The transcription and translation inhibitor 8-Chloro-Adenosine (8-Cl-Ado), currently in clinical trials, is metabolized into its cytotoxic form 8-Cl-ATP causing a parallel decrease of the cellular ATP pool. Treatment with 0.5 µM 17-AAG for 8 hours resulted in the induction of all HSP transcript and protein levels in the three MM cell lines evaluated. In the combination treatment, 10 µM 8-Cl-Ado for 20 hours did not abrogate the induction of HSP mRNA or protein levels. Since cellular bioenergy is necessary for the stabilization of oncoproteins by HSP90, immunoblot assays analyzing for expression levels of client proteins such as STAT3, Raf-1, and Akt were performed. Immunoblot assays detecting for the phosphorylation status of the translation repressor 4E-BP1, whose activity is modulated by upstream kinases sensitive to changes in ATP levels, were also performed. The hypophosphorylated state of 4E-BP1 leads to translation repression. Data indicated that treatment with 17-AAG alone resulted in a minor (<10%) change in STAT3, Raf-1, and Akt protein levels, while no change was observed for 4E-BP1. The combination treatment resulted in more than 50% decrease of the client protein levels and hypophosphorylation of 4E-BP1 in all MM cell lines. Treatment with 8-Cl-Ado alone resulted in less than 30% decrease in client protein levels as well as a decrease in 4E-BP1 phosphorylation. Cytotoxic evaluation of 8-Cl-Ado in combination with 17-AAG resulted in more than additive cytotoxicity when drugs were combined in a sequential manner. In summary, these data suggest that the mechanism-based combination of agents that target transcription, translation, or decrease cellular bioenergy with 17-AAG results in increase cytotoxicity when compared to the single agents. Such combination strategies may be applied in the clinic since these drugs are established chemotherapeutic agents or currently in clinical trials.

Molecular mechanism by which the nucleoid occlusion factor, SlmA, keeps cytokinesis in check.

In Escherichia coli, cytokinesis is orchestrated by FtsZ, which forms a Z-ring to drive septation. Spatial and temporal control of Z-ring formation is achieved by the Min and nucleoid occlusion (NO) systems. Unlike the well-studied Min system, less is known about the anti-DNA guillotining NO process. Here, we describe studies addressing the molecular mechanism of SlmA (synthetic lethal with a defective Min system)-mediated NO. SlmA contains a TetR-like DNA-binding fold, and chromatin immunoprecipitation analyses show that SlmA-binding sites are dispersed on the chromosome except the Ter region, which segregates immediately before septation. SlmA binds DNA and FtsZ simultaneously, and the SlmA-FtsZ structure reveals that two FtsZ molecules sandwich a SlmA dimer. In this complex, FtsZ can still bind GTP and form protofilaments, but the separated protofilaments are forced into an anti-parallel arrangement. This suggests that SlmA may alter FtsZ polymer assembly. Indeed, electron microscopy data, showing that SlmA-DNA disrupts the formation of normal FtsZ polymers and induces distinct spiral structures, supports this. Thus, the combined data reveal how SlmA derails Z-ring formation at the correct place and time to effect NO.

Dimensional synthesis of a spherical parallel manipulator based on the evaluation of global performance indexes

In this work, the dimensional synthesis of a spherical Parallel Manipulator (PM) with a -1S kinematic chain is presented. The goal of the synthesis is to find a set of parameters that defines the PM with the best performance in terms of workspace capabilities, dexterity and isotropy. The PM is parametrized in terms of a reference element, and a non-directed search of these parameters is carried out. First, the inverse kinematics and instantaneous kinematics of the mechanism are presented. The latter is found using the screw theory formulation. An algorithm that explores a bounded set of parameters and determines the corresponding value of global indexes is presented. The concepts of a novel global performance index and a compound index are introduced. Simulation results are shown and discussed. The best PMs found in terms of each performance index evaluated are locally analyzed in terms of its workspace and local dexterity. The relationship between the performance of the PM and its parameters is discussed, and a prototype with the best performance in terms of the compound index is presented and analyzed.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Advanced Control Strategies for a 6 DoF Hydraulic Parallel Robot Based on the Dynamic Model

Nowadays robots have made their way into real applications that were prohibitive and unthinkable thirty years ago. This is mainly due to the increase in power computations and the evolution in the theoretical field of robotics and control. Even though there is plenty of information in the current literature on this topics, it is not easy to find clear concepts of how to proceed in order to design and implement a controller for a robot. In general, the design of a controller requires of a complete understanding and knowledge of the system to be controlled. Therefore, for advanced control techniques the systems must be first identified. Once again this particular objective is cumbersome and is never straight forward requiring of great expertise and some criteria must be adopted. On the other hand, the particular problem of designing a controller is even more complex when dealing with Parallel Manipulators (PM), since their closed-loop structures give rise to a highly nonlinear system. Under this basis the current work is developed, which intends to resume and gather all the concepts and experiences involve for the control of an Hydraulic Parallel Manipulator. The main objective of this thesis is to provide a guide remarking all the steps involve in the designing of advanced control technique for PMs. The analysis of the PM under study is minced up to the core of the mechanism: the hydraulic actuators. The actuators are modeled and experimental identified. Additionally, some consideration regarding traditional PID controllers are presented and an adaptive controller is finally implemented. From a macro perspective the kinematic and dynamic model of the PM are presented. Based on the model of the system and extending the adaptive controller of the actuator, a control strategy for the PM is developed and its performance is analyzed with simulation.

Parallel-up structure evidences the molecular directionality during biosynthesis of bacterial cellulose

The “parallel-up” packing in cellulose Iα and Iβ unit cells was experimentally demonstrated by a combination of direct-staining the reducing ends of cellulose chains and microdiffraction-tilting electron crystallographic analysis. Microdiffraction investigation of nascent bacterial cellulose microfibrils showed that the reducing end of the growing cellulose chains points away from the bacterium, and this provides direct evidence that polymerization by the cellulose synthase takes place at the nonreducing end of the growing cellulose chains. This mechanism is likely to be valid also for a number of processive glycosyltransferases such as chitin synthases, hyaluronan synthases, and proteins involved in the synthesis of nodulation factor backbones.

Mice mutant for glucokinase regulatory protein exhibit decreased liver glucokinase: A sequestration mechanism in metabolic regulation

The importance of glucokinase (GK; EC 2.7.1.12) in glucose homeostasis has been demonstrated by the association of GK mutations with diabetes mellitus in humans and by alterations in glucose metabolism in transgenic and gene knockout mice. Liver GK activity in humans and rodents is allosterically inhibited by GK regulatory protein (GKRP). To further understand the role of GKRP in GK regulation, the mouse GKRP gene was inactivated. With the knockout of the GKRP gene, there was a parallel loss of GK protein and activity in mutant mouse liver. The loss was primarily because of posttranscriptional regulation of GK, indicating a positive regulatory role for GKRP in maintaining GK levels and activity. As in rat hepatocytes, both GK and GKRP were localized in the nuclei of mouse hepatocytes cultured in low-glucose-containing medium. In the presence of fructose or high concentrations of glucose, conditions known to relieve GK inhibition by GKRP in vitro, only GK was translocated into the cytoplasm. In the GKRP-mutant hepatocytes, GK was not found in the nucleus under any tested conditions. We propose that GKRP functions as an anchor to sequester and inhibit GK in the hepatocyte nucleus, where it is protected from degradation. This ensures that glucose phosphorylation is minimal when the liver is in the fasting, glucose-producing phase. This also enables the hepatocytes to rapidly mobilize GK into the cytoplasm to phosphorylate and store or metabolize glucose after the ingestion of dietary glucose. In GKRP-mutant mice, the disruption of this regulation and the subsequent decrease in GK activity leads to altered glucose metabolism and impaired glycemic control.

Estrogen-induced transcription of the progesterone receptor gene does not parallel estrogen receptor occupancy

The activation of the silent endogenous progesterone receptor (PR) gene by 17-β-estradiol (E2) in cells stably transfected with estrogen receptor (ER) was used as a model system to study the mechanism of E2-induced transcription. The time course of E2-induced PR transcription rate was determined by nuclear run-on assays. No marked effect on specific PR gene transcription rates was detected at 0 and 1 h of E2 treatment. After 3 h of E2 treatment, the PR mRNA synthesis rate increased 2.0- ± 0.2-fold and continued to increase to 3.5- ± 0.4-fold by 24 h as compared with 0 h. The transcription rate increase was followed by PR mRNA accumulation. No PR mRNA was detectable at 0, 1, and 3 h of E2 treatment. PR mRNA accumulation was detected at 6 h of E2 treatment and continued to accumulate until 18 h, the longest time point examined. Interestingly, this slow and gradual transcription rate increase of the endogenous PR gene did not parallel binding of E2 to ER, which was maximized within 30 min. Furthermore, the E2–ER level was down-regulated to 15% at 3 h as compared with 30 min of E2 treatment and remained low at 24 h of E2 exposure. These paradoxical observations indicate that E2-induced transcription activation is more complicated than just an association of the occupied ER with the transcription machinery.

Mitochondrial control of calcium-channel gating: A mechanism for sustained signaling and transcriptional activation in T lymphocytes

In addition to their well-known functions in cellular energy transduction, mitochondria play an important role in modulating the amplitude and time course of intracellular Ca2+ signals. In many cells, mitochondria act as Ca2+ buffers by taking up and releasing Ca2+, but this simple buffering action by itself often cannot explain the organelle's effects on Ca2+ signaling dynamics. Here we describe the functional interaction of mitochondria with store-operated Ca2+ channels in T lymphocytes as a mechanism of mitochondrial Ca2+ signaling. In Jurkat T cells with functional mitochondria, prolonged depletion of Ca2+ stores causes sustained activation of the store-operated Ca2+ current, ICRAC (CRAC, Ca2+ release-activated Ca2+). Inhibition of mitochondrial Ca2+ uptake by compounds that dissipate the intramitochondrial potential unmasks Ca2+-dependent inactivation of ICRAC. Thus, functional mitochondria are required to maintain CRAC-channel activity, most likely by preventing local Ca2+ accumulation near sites that govern channel inactivation. In cells stimulated through the T-cell antigen receptor, acute blockade of mitochondrial Ca2+ uptake inhibits the nuclear translocation of the transcription factor NFAT in parallel with CRAC channel activity and [Ca2+]i elevation, indicating a functional link between mitochondrial regulation of ICRAC and T-cell activation. These results demonstrate a role for mitochondria in controlling Ca2+ channel activity and signal transmission from the plasma membrane to the nucleus.

Chronic morphine induces the concomitant phosphorylation and altered association of multiple signaling proteins: A novel mechanism for modulating cell signaling

Traditional mechanisms thought to underlie opioid tolerance include receptor phosphorylation/down-regulation, G-protein uncoupling, and adenylyl cyclase superactivation. A parallel line of investigation also indicates that opioid tolerance development results from a switch from predominantly opioid receptor Giα inhibitory to Gβγ stimulatory signaling. As described previously, this results, in part, from the increased relative abundance of Gβγ-stimulated adenylyl cyclase isoforms as well as from a profound increase in their phosphorylation [Chakrabarti, S., Rivera, M., Yan, S.-Z., Tang, W.-J. & Gintzler, A. R. (1998) Mol. Pharmacol. 54, 655–662; Chakrabarti, S., Wang, L., Tang, W.-J. & Gintzler, A. R. (1998) Mol. Pharmacol. 54, 949–953]. The present study demonstrates that chronic morphine administration results in the concomitant phosphorylation of three key signaling proteins, G protein receptor kinase (GRK) 2/3, β-arrestin, and Gβ, in the guinea pig longitudinal muscle myenteric plexus tissue. Augmented phosphorylation of all three proteins is evident in immunoprecipitate obtained by using either anti-GRK2/3 or Gβ antibodies, but the phosphorylation increment is greater in immunoprecipitate obtained with Gβ antibodies. Analyses of coimmunoprecipitated proteins indicate that phosphorylation of GRK2/3, β-arrestin, and Gβ has varying consequences on their ability to associate. As a result, increased availability of and signaling via Gβγ could occur without compromising the membrane content (and presumably activity) of GRK2/3. Induction of the concomitant phosphorylation of multiple proteins in a multimolecular complex with attendant modulation of their association represents a novel mechanism for increasing Gβγ signaling and opioid tolerance formation.