The rise and fall in the price of food, fuel and manufactured goods : interdependency between prices and technology determining comparative advantages and development paths

Green innovation, which enables us to extract energy from food crops, caused a food shortage in 2008. Countries suffering severe damage started to reconsider their agricultural policy with the aim of becoming more autonomous. The food price hike of the time looks like a reversal of the celebrated Singer-Prebisch thesis proposed in the 1950s. This paper examines the consequences of this trend on the comparative advantages and development strategies of developing countries. For that purpose, first, trends and short-run fluctuations in the prices of fuel and bio-energy crops are investigated. It is shown that the price series of fuels and the crops are synchronized only after the fuel extracting technology came into effect. Second, the reversal of the Singer-Prebisch thesis is underpinned by the generic form of an endogenous growth model developed by Rebelo (1991). It is shown that as an economy grows, appreciation of the non-reproducible, such as mineral resources and raw labor, over the reproducible, such as capital goods, is the norm rather than an anomaly. Third, the consequences of the food price hike and underlying capital accumulation on the development strategies of labor-abundant and low-income countries are explored. It is concluded that the impact of the food price hikes on the alteration of a development strategy is only incremental, without reinforcement from raw-labor-saving innovation. A case study of inventions by JUKI Corporation, a world-leader in the sewing machine market exemplifies the fact that, of all the major inventions the company have made, raw-labor-saving inventions have not dominated, although JUKI's machines are sold to one of the most raw-labor-intensive industries.

Optimal fits of diffusion constants from single-time data points of Brownian trajectories

Experimental methods based on single particle tracking (SPT) are being increasingly employed in the physical and biological sciences, where nanoscale objects are visualized with high temporal and spatial resolution. SPT can probe interactions between a particle and its environment but the price to be paid is the absence of ensemble averaging and a consequent lack of statistics. Here we address the benchmark question of how to accurately extract the diffusion constant of one single Brownian trajectory. We analyze a class of estimators based on weighted functionals of the square displacement. For a certain choice of the weight function these functionals provide the true ensemble averaged diffusion coefficient, with a precision that increases with the trajectory resolution.

Electricity price forecasting accounting for renewable energies: optimal combined forecasts

Electricity price forecasting is an interesting problem for all the agents involved in electricity market operation. For instance, every profit maximisation strategy is based on the computation of accurate one-day-ahead forecasts, which is why electricity price forecasting has been a growing field of research in recent years. In addition, the increasing concern about environmental issues has led to a high penetration of renewable energies, particularly wind. In some European countries such as Spain, Germany and Denmark, renewable energy is having a deep impact on the local power markets. In this paper, we propose an optimal model from the perspective of forecasting accuracy, and it consists of a combination of several univariate and multivariate time series methods that account for the amount of energy produced with clean energies, particularly wind and hydro, which are the most relevant renewable energy sources in the Iberian Market. This market is used to illustrate the proposed methodology, as it is one of those markets in which wind power production is more relevant in terms of its percentage of the total demand, but of course our method can be applied to any other liberalised power market. As far as our contribution is concerned, first, the methodology proposed by García-Martos et al(2007 and 2012) is generalised twofold: we allow the incorporation of wind power production and hydro reservoirs, and we do not impose the restriction of using the same model for 24h. A computational experiment and a Design of Experiments (DOE) are performed for this purpose. Then, for those hours in which there are two or more models without statistically significant differences in terms of their forecasting accuracy, a combination of forecasts is proposed by weighting the best models(according to the DOE) and minimising the Mean Absolute Percentage Error (MAPE). The MAPE is the most popular accuracy metric for comparing electricity price forecasting models. We construct the combi nation of forecasts by solving several nonlinear optimisation problems that allow computation of the optimal weights for building the combination of forecasts. The results are obtained by a large computational experiment that entails calculating out-of-sample forecasts for every hour in every day in the period from January 2007 to Decem ber 2009. In addition, to reinforce the value of our methodology, we compare our results with those that appear in recent published works in the field. This comparison shows the superiority of our methodology in terms of forecasting accuracy.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Hacia una arquitectura de procesos : transformaciones disciplinares a través de la Computación en los modelos de Alexander, Negroponte y Price

La premisa inicial de la tesis examina cómo las secuelas de Segunda Guerra mundial motivaron una revisión general de la Ciencia y procuraron una nueva relación entre el hombre y su entorno. Matemáticas, Física y Biología gestaron las Ciencias de la Computación como disciplina de convergencia. En un momento de re-definición del objeto científico, una serie de arquitectos vislumbraron la oportunidad para transformar ciertas convenciones disciplinares. Mediante la incorporación de ontologías y procedimientos de cibernética y computación, trazaron un nuevo espacio arquitectónico. Legitimados por un despegue tecnológico incuestionable, desafían los límites de la profesión explorando campos abiertos a nuevos programas y acciones; amplían el dominio natural de la Arquitectura más allá del objeto(terminado) hacia el proceso(abierto). Se da inicio a la tesis describiendo los antecedentes que conducen a ese escenario de cambio. Se anotan aspectos de Teoría de Sistemas, Computación, Biología y de ciertos referentes de Arquitectura con relevancia para esa nuevo planteamiento. En esos antecedentes residen los argumentos para orientar la disciplina hacia el trabajo con procesos. La linea argumental central del texto aborda la obra de Christopher Alexander, Nicholas Negroponte y Cedric Price a través de una producción teórica y práctica transformada por la computación, y examina la contribución conceptual de cada autor. El análisis comparado de sus modelos se dispone mediante la disección de tres conceptos convergentes: Sistema, Código y Proceso. La discusión crítica se articula por una triangulación entre los autores, donde se identifican comparando por pares las coincidencias y controversias entre ellos. Sirve este procedimiento al propósito de tender un puente conceptual con el escenario arquitectónico actual estimando el impacto de sus propuestas. Se valora su contribución en la deriva del programa cerrado a la especulación , de lo formal a lo informal, de lo único a lo múltiple; del estudio de arquitectura al laboratorio de investigación. Para guiar ese recorrido por la significación de cada autor en el desarrollo digital de la disciplina, se incorporan a la escena dos predicados esenciales; expertos en computación que trabajaron de enlace entre los autores, matizando el significado de sus modelos. El trabajo de Gordon Pask y John Frazer constituye el vehículo de transmisión de los hallazgos de aquellos años, prolonga los caminos iniciados entonces, en la arquitectura de hoy y la que ya se está diseñando para mañana. ABSTRACT The initial premise of the thesis examines how the aftermath of second world war motivated a general revision of science and procure the basis of a new relation between mankind and its environment. Mathematics, Physics, and Biology gave birth to the Computer Sciences as a blend of different knowledge and procedures. In a time when the object of major sciences was being redefined, a few architects saw a promising opportunity for transforming the Architectural convention. By implementing the concepts, ontology and procedures of Cybernetics, Artificial Intelligence and Information Technology, they envisioned a new space for their discipline. In the verge of transgression three prescient architects proposed complete architectural systems through their writings and projects; New systems that challenged the profession exploring open fields through program and action, questioning the culture of conservatism; They shifted architectural endeavor from object to process. The thesis starts describing the scientific and architectural background that lead to that opportunity, annotating aspects of Systems Theory, Computing, Biology and previous Architecture form the process perspective. It then focuses on the Works of Christopher Alexander, Nicholas Negroponte and Cedric Price through their work, and examines each authors conceptual contribution. It proceeds to a critical analysis of their proposals on three key converging aspects: system, architectural encoding and process. Finally, the thesis provides a comparative discussion between the three authors, and unfolds the impact of their work in todays architectural scenario. Their contribution to shift from service to speculation, from formal to informal , from unitary to multiple; from orthodox architecture studio to open laboratories of praxis through research. In order to conclude that triangle of concepts, other contributions come into scene to provide relevant predicates and complete those models. A reference to Gordon Pask and John Frazer is then provided with particular interest in their role as link between those pioneers and todays perspective, pushing the boundaries of both what architecture was and what it could become.

Modeling the Real-Time Use of Reserves in the Joint Energy and Reserve Hourly Scheduling of a Pumped Storage Plant

This paper studies the impact that different approaches of modeling the real-time use of the secondary regulation reserves have in the joint energy and reserve hourly scheduling of a price-taker pumped-storage hydropower plant. The unexpected imbalance costs due to the error between the forecasted real-time use of the reserves and the actual value are also studied and evaluated for the different approaches. The proposed methodology is applied to a daily-cycle and closed-loop pumped-storage hydropower plant. Preliminary results show that the deviations in the water volume at the end of the day are important when the percentage of the real-time use of reserves is unknown in advance, and also that the total income in all approaches after correcting these deviations is significantly lower than the maximum theoretical income.

Brexit or not? Time for the EU to move. EPC Commentary, 8 September 2014

The deteriorating relationship between the United Kingdom (UK) and the rest of the EU, including the prospect of a referendum on EU membership, would have dominated the Union’s agenda had it not been for the economic/financial crisis, followed by the external crisis which we are now facing in the East. Precisely because of these crises, it is now time for the incoming European Commission to take the bull by the horns and ensure that the EU can move on from a potential referendum and its possible outcomes. The June European Council noted that “the UK raised some concerns related to the future development of the EU. These concerns will need to be addressed. In this context, the European Council noted that the concept of ever closer union allows for different paths of integration for different countries, allowing those that want to deepen integration to move ahead, while respecting the wish of those who do not want to deepen any further.” While the EU has, arguably, successfully developed at different speeds for decades, to address the UK’s (fundamental) concerns, it is now time to work out whether and how the UK can be accommodated, and what this would mean in practice. UK membership is desirable but not at any price, so the aim should be to keep the UK in, while also ensuring that the principles on which the EU is built are protected. There will need to be a modus operandi which enables the EU and in particular, the Eurozone, to continue to make progress in addressing the shortcomings of European integration and European Monetary Union (EMU) in particular, while at the same time offering a reform package that can satisfy the UK. This does not necessarily mean that all EMU reforms have to be within the EU framework: additional intergovernmental arrangements could also be a possibility. However, this could add to the complexity and inefficiency of the system, as well as sidelining the supranational element of EU governance which will be needed to make EMU function.

At any price: Russia is embarking on the construction of South Stream. OSW Commentary No. 98, 2012-12-07

Gazprom is determined to continue its efforts to build the South Stream gas pipeline regardless of the slump on the European gas market and the fact that there is sufficient capacity already in the existing transport infrastructure. The official inauguration of the maritime section of South Stream was held on 7 December this year, but the construction itself will commence in 2014. The agreements concluded so far, both intergovernmental and between corporations, are necessary for the launch of the construction of the new pipeline, but still do not guarantee that the project will be completed on time. First of all, some legal problems have yet to be resolved, such as the evaluation of the compliance of the planned actions with the ‘third energy package’ or the fact that ecological surveys required under European law need to be carried out. Secondly, given the present situation on the European gas market and medium-term forecasts, the high cost of implementation of this project and the maintenance expenses of existing pipelines – which are not being used to full capacity – the new project seems to be unfeasible. However, Gazprom’s determination in its efforts to build the pipeline proves that Russia is ready to take a high economic risk to maintain its dominant position on the European gas supply market; it will restrict the possibilities of alternative infrastructural projects being implemented (above all, the EU’s Southern Corridor) and use the construction of new pipelines as an instrument of political pressure on the present transit countries (especially Ukraine).

The Market for Tractors in the EU: Price Differences and Convergence. Factor Markets Working Documents No. 35, February 2013

This study evaluates the degree of segmentation of the market for agricultural machinery and equipment in the EU. We focus on agricultural tractors, the most common and biggest investment in machinery and equipment in the agricultural sector. By using country price data for individual tractor models, we test the law of one price, i.e. the existence of a common price for tractors across EU member states. We find that significant price differences exist, yet unlike most other studies we find that large price deviations are penalised within a short time. The study also shows that transport costs are an important source of price differences, as domestic production leads to lower prices on the domestic market and as price convergence is negatively correlated with distance. Finally, price differences should not solely be understood from a geographical perspective, as evidence supports the idea that farmers’ buying power is significant in explaining price differences within countries.

The Eurasian Economic Union: a time of crisis. OSW COMMENTARY NUMBER 195/27.01.2016

The Eurasian Economic Union (EaEU), a project forced through by Russia which links it to Kazakhstan, Belarus, Armenia and Kyrgyzstan, is currently struggling with serious problems. The economic crisis in Russia – mainly caused by the fall in the price of oil on world markets and exacerbated by sanctions imposed by Western countries in connection with the Ukraine conflict – is affecting these uncompetitive post-Soviet economies which are dependent on Russia. This has resulted in increased economic and political tension among the members of the EaEU. From Russia’s point of view, however, the EaEU project remains useful, because it is not economic integration that is Moscow’s priority. The Union remains its most important instrument for implementing the Kremlin’s geo-political objectives, in particular maintaining its sphere of influence and preventing post-Soviet countries from integrating with the West, as well as restricting their rapprochement with China. Moscow is pushing for the EaEU to include new countries, strengthening its tools for political dominance within the Union, and promoting its project on the international stage. However, the future of this project will depend on both the continued determination of the Kremlin, and whether the other countries can change the rules for integration by taking advantage of the current crisis.

[Minor publications prepared under the chairmanship of Ira M. Price.

[First annual] report.-- Second annual report.-- Seventh annual report.-- Bulletin no. 10. War-time programs of church service.-- Bulletin no. 12. Religious education throught activity.-- The laymen and the kingdom. [Publication] no. 22, issued by the Brotherhood Council of the American Baptist Convention.

Holston Methodism : from its origin to the present time.

v. 1. From the introduction of Methodism into the Holston country to the year 1804 -- v. 2. From the year 1804 to the year 1824 -- v. 3. From the year 1824 to the year 1844 -- v. 4. From the year 1844 to the year 1870 / with an introd. by the Rev. David Sullins -- v. 5. From the year 1870 to the year 1897 / with an introd. by R.G. Waterhouse.

The Promise and the Price of Contact: Puyallup Indian Acculturation, Federal Indian Policy and the City of Tacoma, 1832-1909

Thesis (Ph.D.)--University of Washington, 2016-06

The price elasticity of the Euro to movements in foreign reserves through European Central Bank intevention

The Euro has been used as the largest weighting element in a basket of currencies for forex arrangements adopted by several Central European countries outside the European Union (EU). The paper uses a new time-series approach to examine the relationship between the Euro exchange rate and the level of foreign reserves. It employs Zero-no-zero (ZNZ) patterned vector error-correction (VECM) modelling to investigate Granger causal relations among foreign reserves, the European Monetary Union money supply and the Euro exchange rate. The findings confirm that foreign reserves may influence movements in the Euro's exchange rate. Further, ZNZ patterned VECM modelling with exogenous variables is used to estimate the amount of foreign reserves currently required in order to again achieve a targetted Euro exchange rate