Plasmonic nanotips for on-chip nanoscale confinement of light

We demonstrate the on-chip nanoscale focusing of surface plasmons in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. Enhancing light matter interactions is discussed. © 2011 Optical Society of America.

On chip plasmonic enhanced silicon schottky detector for telecom wavelengths

We demonstrate an integrated on-chip plasmonic enhanced Schottky detector for telecom wavelengths based on the internal photoemission process. This CMOS compatible device may serve as a promising alternative to the Si-Ge detectors. © 2011 Optical Society of America.

16 chip, 18 Gchips/s walsh-code implementation of an ECDMA access network using two time-shifted FIR filters

We demonstrate for the first time an electronically processed Walsh Code with 16 chips at 18Gchip/s. An auto-cross correlation ratio of 18.1dB is achieved between two orthogonal codes after transmission over 10km of SMF. © 2009 OSA.

On-chip focusing of light by metallic nanotip

We present a numerical simulations, fabrication and experimental results for on-chip focusing of surface plasmon polaritons (SPPs) in metal nanotip coupled to the silicon waveguide. © 2011 Optical Society of America.

On-chip tunable micro-ring resonator based on digital microfluidics platform

We demonstrate the tunability of a silicon nitride micro-resonator using the concept of Digital Microfluidics. Our system allows driving micro-droplets on-chip, enabling the control of the effective refractive index at the vicinity of the resonator. © 2010 OSA/FiO/LS 2010.

On-chip focusing of light by Metallic Nanotip

We investigate numerically and experimentally the on-chip nanoscale focusing of surface plasmon polaritons (SPPs) in metallic nanotip coupled to the silicon waveguide. Strong field enhancement is observed at the apex of the tip. © 2010 Optical Society of America.

Identification and characterization of Bacillus anthracis by multiplex PCR on DNA chip

Bacillus anthracis can be identified by detecting virulence factor genes located on two plasmids, pXO1 and pXO2. Combining multiplex PCR with arrayed anchored primer PCR and biotin-avidin alkaline phosphatase indicator system, we developed a qualitative DNA chip method for characterization of B. anthracis, and simultaneous confirmation of the species identity independent of plasmid contents. The assay amplifies pag gene (in pXO1), cap gene (in pXO2) and Ba813 gene (a B. anthracis specific chromosomal marker), and the results were indicated by an easy-to-read profile based on the color reaction of alkaline phosphatase. About 1 pg of specific DNA fragments on the chip wells could be detected after PCR. With the proposed method, the avirulent (pXO1(+)/2(-), pXO1(-)/2(+) and pXO1(-)/2(-)) strains of B. anthracis and distinguished 'anthrax-like' strains from other B. cereus group bacteria were unambiguously identified, while the genera other than Bacillus gave no positive signal. (C) 2004 Elsevier B.V. All rights reserved.

Oligonucleotide ligation assay-based DNA chip for multiplex detection of single nucleotide polymorphism

An oligonucleotide ligation assay-based DNA chip has been developed to detect single nucleotide polymorphism. Synthesized nonamers, complementary to the flanking sequences of the mutation sites in target DNA, were immobilized onto glass slides through disulfide bonds on their 5' terminus. Allele-specific pentamers annealed adjacent to the nonamers on the complementary target DNA, containing 5'-phosphate groups and biotin labeled 3'-ends, were mixed with the target DNA in tube. Ligation reactions between nonamers and pentamers were carried out on chips in the presence of T4 DNA ligase. Ligation products were directly visualized on chips through enzyme-linked assay. The effect of G:T mismatch at different positions of pentamers on the ligation were evaluated. The results showed that any mismatch between pentamer and the target DNA could lead to the decrease of ligation, which can be detected easily. The established approach was further used for multiplex detection of mutations in rpoB gene of rifampin-resistant Mycobacterium tuberculosis clinical isolates. (C) 2003 Elsevier B.V. All rights reserved.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.