Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

A clocking technique with power savings in virtex-based pipelined designs

This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

TCL/TK for EDA tools

Tcl/Tk scripting language has become the de-facto standard for EDA tools. This paper explains how to start working with Tcl/Tk using simple examples. Two complete applications are presented to show in more detail the capabilities of the language. In one script average power consumption of a digital system is automated. A second script creates a virtual display driven by the simulation of a graphic card.

Generic construction of monitors for floating point unit designs

This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.

Analise epistemológica do processo educacional brasileiro a partir da evolução da maquina

O presente trabalho parte do pressuposto de que o desenvolvimento das ideias e ações humanas é indissociável do processo de evolução da máquina, destacando o aspecto interativo aí existente: a mente que concebe a máquina e que, por sua vez, passa a servir de modelo para, essa mesma mente construir a sua visão de mundo. O objetivo principal consiste em analisar as bases epistemológicas do processo educacional brasileiro a partir do desenvolvimento da própria máquina, o qual, segundo a teoria aqui adotada, subdivide-se em quatro etapas: a máquina Pré-Clássica, a máquina Clássica, a máquina Cibernética e a máquina Informacional. A hipótese aqui apresentada, e no final confirmada, é a de que, apesar de hoje o mundo estar subjugado às propriedades da maquina informacional, na estrutura do processo educacional brasileiro predominam as características epistêmicas da maquina clássica, devido a nossa educação continuar arraigada em aspectos constitutivos dessa máquina: em sua Iógica (linear), em seu ritmo (padrão de comportamento) e em sua morfologia (elementarização). Através desse estudo procura se evidencia que transformações se operaram (ou não) no processo educacional brasileiro e a necessidade de uma redefinição conceitual e metodológica da própria educação, de forma que se minimize a distância entre a mesma e o progresso tecnológico.

Desenvolvimento de sistemas embarcados para redes de sensores e atuadores sem fio aplicadas em unidades de elevação de petróleo do tipo Plunger-Lift

The Wireless Sensor Networks (WSN) methods applied to the lifting of oil present as an area with growing demand technical and scientific in view of the optimizations that can be carried forward with existing processes. This dissertation has as main objective to present the development of embedded systems dedicated to a wireless sensor network based on IEEE 802.15.4, which applies the ZigBee protocol, between sensors, actuators and the PLC (Programmable Logic Controller), aiming to solve the present problems in the deployment and maintenance of the physical communication of current elevation oil units based on the method Plunger-Lift. Embedded systems developed for this application will be responsible for acquiring information from sensors and control actuators of the devices present at the well, and also, using the Modbus protocol to make this network becomes transparent to the PLC responsible for controlling the production and delivery information for supervisory SISAL

Controle preditivo robusto baseado em desigualdades matriciais lineares aplicado a um sistema de tanques acoplados

This work deals with an on-line control strategy based on Robust Model Predictive Control (RMPC) technique applied in a real coupled tanks system. This process consists of two coupled tanks and a pump to feed the liquid to the system. The control objective (regulator problem) is to keep the tanks levels in the considered operation point even in the presence of disturbance. The RMPC is a technique that allows explicit incorporation of the plant uncertainty in the problem formulation. The goal is to design, at each time step, a state-feedback control law that minimizes a 'worst-case' infinite horizon objective function, subject to constraint in the control. The existence of a feedback control law satisfying the input constraints is reduced to a convex optimization over linear matrix inequalities (LMIs) problem. It is shown in this work that for the plant uncertainty described by the polytope, the feasible receding horizon state feedback control design is robustly stabilizing. The software implementation of the RMPC is made using Scilab, and its communication with Coupled Tanks Systems is done through the OLE for Process Control (OPC) industrial protocol

Paraconsistent Autonomous Mobile Robot Emmy III

This work presents some improvements regarding to the autonomous mobile robot Emmy based on Paraconsistent Annotated Evidential Logic ET. A discussion on navigation system is presented.

Desenvolvimento de um programa computacional destinado à unidade móvel de ensaio na barra de tração (umeb) para a avaliação do desempenho de tratores

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desenvolvimento de um sistema de posicionamento automático para painéis fotovoltaicos

Pós-graduação em Agronomia (Energia na Agricultura) - FCA

Automação do manejo alimentar na engorda de tilápias criadas em tanque-rede

Pós-graduação em Zootecnia - FMVZ

Informação e abdução no processo de descoberta científica

Pós-graduação em Filosofia - FFC

Un distributore intelligente di bevande alla spina con sistema di pagamento basato su Bitcoin

I distributori automatici sono attualmente molto diffusi perché permettono di automatizzare l'erogazione di un prodotto o servizio senza la necessità di avere una persona addetta a quello scopo. Questa tesi si pone l'obiettivo di progettare e sviluppare un’applicazione per sistemi embedded Linux che consenta agli utenti di richiedere, in modo autonomo, il pagamento tramite Bitcoin con la successiva erogazione di bevande alla spina.

Magnetic Flip Flops for Space Applications

The radiation environment of space presents a significant threat to the reliability of nonvolatile memory technologies. Ionizing radiation disturbs the charge stored on floating gates, and cosmic rays can permanently damage thin oxides. A new memory technology based on the magnetic tunneling junction (MTJ) appears to offer superior resistance to radiation effects and virtually unlimited write endurance. A magnetic flip flop has a number of potential applications, such as the configuration memory in field-programmable logic devices. However, using MTJs in a flip flop requires radically different circuitry for storing and retrieving data. New techniques are needed to insure that magnetic flip flops are reliable in the radiation environment of space. We propose a new radiation-tolerant magnetic flip flop that uses the inherent resistance of the MTJ to increase its immunity to single event upset and employs a robust “Pac-man” magnetic element.