A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.

Gate of Serranos [Material gráfico] :Valencia

Resumen: Descripción: vista de las Torres de Serranos

Vista de la puerta de Serranos de Valencia [Material gráfico] =Vue de la Porte de Serranos à Valence=View of the Gate of Serranos at Valencia

Datos de publicación tomados de la obra a la que pertenece

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.

Vista de la puerta de entrada de la fortaleza de Xativa [ [Material gráfico]= Vue de la porte d'entrèe de la forteresse de Xativa, et d'une partie de la ville de St. Philippe = View of the great gate of the fortress of Xativa, and of a part of the town of St. Philip

Datos de publicación tomados de la obra a la que pertenece

DNA transport by a type II topoisomerase: direct evidence for a two-gate mechanism.

Recent biochemical and crystallographic results suggest that a type II DNA topoisomerase acts as an ATP-modulated clamp with two sets of jaws at opposite ends: a DNA-bound enzyme can admit a second DNA through one set of jaws; upon binding ATP, this DNA is passed through an enzyme-mediated opening in the first DNA and expelled from the enzyme through the other set of jaws. Experiments based on the introduction of reversible disulfide links across one dimer interface of yeast DNA topoisomerase II have confirmed this mechanism. The second DNA is found to enter the enzyme through the gate formed by the N-terminal parts of the enzyme and leave it through the gate close to the C termini.

Long Walk to Laboratory (Jenny [Jerry] of '79 in gate)

Northwest corner of campus with old fenceposts

Golden Gate bridge, California tolls on government traffic : hearings ... 78th Congress, 1st session on H.R. 877, a bill to authorize the charging of tolls for the passage or transit of government traffic over the Golden Gate bridge.

Hearing held March 9, 1943.