Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Chromophore-assisted light inactivation and self-organization of microtubules and motors

Chromophore-assisted light inactivation (CALI) offers the only method capable of modulating specific protein activities in localized regions and at particular times. Here, we generalize CALI so that it can be applied to a wider range of tasks. Specifically, we show that CALI can work with a genetically inserted epitope tag; we investigate the effectiveness of alternative dyes, especially fluorescein, comparing them with the standard CALI dye, malachite green; and we study the relative efficiencies of pulsed and continuous-wave illumination. We then use fluorescein-labeled hemagglutinin antibody fragments, together with relatively low-power continuous-wave illumination to examine the effectiveness of CALI targeted to kinesin. We show that CALI can destroy kinesin activity in at least two ways: it can either result in the apparent loss of motor activity, or it can cause irreversible attachment of the kinesin enzyme to its microtubule substrate. Finally, we apply this implementation of CALI to an in vitro system of motor proteins and microtubules that is capable of self-organized aster formation. In this system, CALI can effectively perturb local structure formation by blocking or reducing the degree of aster formation in chosen regions of the sample, without influencing structure formation elsewhere.

Virus-sized self-assembling lamellar complexes between plasmid DNA and cationic micelles promote gene transfer

Gene therapy is based on the vectorization of genes to target cells and their subsequent expression. Cationic amphiphile-mediated delivery of plasmid DNA is the nonviral gene transfer method most often used. We examined the supramolecular structure of lipopolyamine/plasmid DNA complexes under various condensing conditions. Plasmid DNA complexation with lipopolyamine micelles whose mean diameter was 5 nm revealed three domains, depending on the lipopolyamine/plasmid DNA ratio. These domains respectively corresponded to negatively, neutrally, and positively charged complexes. Transmission electron microscopy and x-ray scattering experiments on complexes originating from these three domains showed that although their morphology depends on the lipopolyamine/plasmid DNA ratio, their particle structure consists of ordered domains characterized by even spacing of 80 Å, irrespective of the lipid/DNA ratio. The most active lipopolyamine/DNA complexes for gene transfer were positively charged. They were characterized by fully condensed DNA inside spherical particles (diameter: 50 nm) sandwiched between lipid bilayers. These results show that supercoiled plasmid DNA is able to transform lipopolyamine micelles into a supramolecular organization characterized by ordered lamellar domains.

Parent Loss in Adolescence and its Impact on Sense of Self: When an Adolescent Boy Loses His Mother.

Adolescence is a developmental phase that involves physical, emotional, and cognitive changes. Often this period is one of transition that requires significant adjustment both with the individual and the family. It is considered to start with puberty, sometime between the ages of 10 and 13, and end with the transition into adulthood (Kruse & Walper, 2008). Puberty is a term that is used to describe the physical changes that generally occur during adolescence. It is an aspect of the changes that occur during the overarching phase of development. Within adolescence, individuals are confronted with many developmental tasks such as establishing an individual identity, making decisions about the future, and moving from dependence on families to independence (Austrian, 2008).There are many changes that occur during adolescence, including sexual maturation and functioning, endocrine developments, and skeletal and muscular changes. Boys will see a growth of body, pubic, and facial hair, their voice will deepen, and they will begin having erections and wet dreams (Kruse & Walper, 2008). The accelerated transformation of this phase generally has an emotional impact and individuals may feel concerned or self-conscious about their appearance. Ausubel, Montemayor, and Svajian (1977) suggest that adolescents may be more sensitive during this period of development. This sensitivity may be in part due to the rapid growth resulting in a sense of awkwardness in appearance and physical coordination.

Parent-Child Interaction and Children's Self-Concept

This study is designed to investigate the relationships between marital communication, the quality of parents' ability to assist their children in joint problem-solving, and children's independent mastery attempts and perceived competence at problem-solving, and behavioral indicators of self-esteem. Couples' skill at regulating their own and their children's negative affect within the marital and parent-child family subsystems is hypothesized to predict the quality of their assistance, or scaffolding behavior, to their children during joint problem-solving. Further, the quality of parental scaffolding behavior is expected to predict children's independent mastery attempts, levels of perceived competence at problemsolving, and behavioral indicators of self-esteem. Families for the study will be those with children between 3 1/2 to six years of age recruited from subjects participating in a longitudinal study of communication in marriage being conducted at the Denver Center for Marital and Family Studies. Families will participate in three interaction tasks designed to tap parental scaffolding behavior during problemsolving with their children. Children will be administered self-report measures to tap their perceived competence at such problem-solving as those in the interaction tasks and parents will complete a questionnaire tapping the behavioral indicators of their child's self-esteem. Family interaction data will be coded with the use of a microanalytic coding system developed by this study, the Parent-Child Interaction Coding System. Marital communication data at three time points, premaritally, during the transition to parenthood , and concurrently, will be obtained from couples' interactions from the longitudinal study. The clinical significance of this study includes implications for training couples how to effectively regulate negative affect and offer their children sensitive assistance during joint problem-solving.

Measurement and prediction of energy expenditure in males during household and garden tasks

Participation in at least 30 min of moderate intensity activity on most days is assumed to confer health benefits. This study accordingly determined whether the more vigorous household and garden tasks (sweeping, window cleaning, vacuuming and lawn mowing) are performed by middle-aged men at a moderate intensity of 3-6 metabolic equivalents (METs) in the laboratory and at home. Measured energy expenditure during self-perceived moderate-paced walking was used as a marker of exercise intensity. Energy expenditure was also predicted via indirect methods. Thirty-six males [Xmacr (SD): 40.0 (3.3) years; 179.5 (6.9) cm; 83.4 (14.0) kg] were measured for resting metabolic rate (RMR) and oxygen consumption (V.O-2) during the five activities using the Douglas bag method. Heart rate , respiratory frequency, CSA (Computer Science Applications) movement counts, Borg scale ratings of perceived exertion and Quetelet's index were also recorded as potential predictors of exercise intensity. Except for vacuuming in the laboratory, which was not significantly different from 3.0 METs (P=0.98), the MET means in the laboratory and home were all significantly greater than 3.0 (Pless than or equal to0.006). The sweeping and vacuuming MET means were significantly higher (P

Pretend play, mirror self-recognition and imitation: A longitudinal investigation through the second year

The aim in the current study was to investigate the emergence of pretend play, mirror self-recognition, synchronic imitation and deferred imitation in normally developing human infants. A longitudinal study was conducted with 98 infants seen at three-monthly intervals from 12 through to 24 months of age. At each session the infants were tested on a range of tasks assessing the four target skills. Deferred imitation was found to emerge prior to synchronic imitation, pretend play and mirror self-recognition. In contrast, the latter three skills emerged between 18 and 21 months and followed similar developmental trajectories. Deferred imitation was found to hold a prerequisite relation with these three skills. Synchronic imitation, pretend play and mirror self-recognition were not closely associated and no prerequisite relations were found between these skills. These findings are discussed in the context of current theories regarding the development of pretend play, mirror self-recognition, synchronic imitation and deferred imitation in the second year. (C) 2004 Elsevier Inc. All rights reserved.

Cross-cultural perceptions in the leadership process: Theoretical perspective on the influence of culture on self-concepts and manager worker attributions

This article examines the influence of culture on the way managers and workers perceive causes of success and failure in organizational tasks. The author argues that selfserving and actor-observer biases, as well as other attribution errors, will be moderated by culture. Specifically, managers and workers with a sociocentric self-concept from high-context cultures may be biased toward external attributions, while managers from low-context cultures with an idiocentric self-concept have a tendency to make more internal attributions. These variations in attributions have consequences that affect both managers and workers. Theoretical propositions and implications for international management practices are discussed. © 2005 Wiley Periodicals, Inc.

Highly-ordered hybrid organic-inorganic isoporous membranes from polymer modified nanoparticles

atomic force microscopy (AFM); atom transfer radical polymerization (ATRP); block copolymers; self-assembly; silica nanoparticles.

The parameterless self-organizing map algorithm

The parameterless self-organizing map (PLSOM) is a new neural network algorithm based on the self-organizing map (SOM). It eliminates the need for a learning rate and annealing schemes for learning rate and neighborhood size. We discuss the relative performance of the PLSOM and the SOM and demonstrate some tasks in which the SOM fails but the PLSOM performs satisfactory. Finally we discuss some example applications of the PLSOM and present a proof of ordering under certain limited conditions.

Self-paced reading and sentence comprehension in Parkinson's disease

Parkinson's disease (PD) is associated with disturbances in sentence processing, particularly for noncanonical sentences. The present study aimed to analyse sentence processing in PD patients and healthy control participants, using a word-by-word self-paced reading task and an auditory comprehension task. Both tasks consisted of subject relative (SR) and object relative (OR) sentences, with comprehension accuracy measured for each sentence type. For the self-paced reading task, reading times (RTs) were also recorded for the non-critical and critical processing regions of each sentence. Analysis of RTs using mixed linear model statistics revealed a delayed sensitivity to the critical processing region of OR sentences in the PD group. In addition, only the PD group demonstrated significantly poorer comprehension of OR sentences compared to SR sentences during an auditory comprehension task. These results may be consistent with slower lexical retrieval in PD, and its influence on the processing of noncanonical sentences. (c) 2005 Elsevier Ltd. All rights reserved.

Changes in brain activation during working memory and facial recognition tasks in patients with bipolar disorder with Lamotrigine monotherapy

Verbal working memory and emotional self-regulation are impaired in Bipolar Disorder (BD). Our aim was to investigate the effect of Lamotrigine (LTG), which is effective in the clinical management of BD, on the neural circuits subserving working memory and emotional processing. Functional Magnetic Resonance Imaging data from 12 stable BD patients was used to detect LTG-induced changes as the differences in brain activity between drug-free and post-LTG monotherapy conditions during a verbal working memory (N-back sequential letter task) and an angry facial affect recognition task. For both tasks, LGT monotherapy compared to baseline was associated with increased activation mostly within the prefrontal cortex and cingulate gyrus, in regions normally engaged in verbal working memory and emotional processing. Therefore, LTG monotherapy in BD patients may enhance cortical function within neural circuits involved in memory and emotional self-regulation. © 2007 Elsevier B.V. and ECNP.

Self-attentional processes in anxiety:an experimental study

Self-attention research has demonstrated a relationship between dispositional self-focus, anxiety proneness and fear arousal. In addition, the effect of self-focus manipulations on approach-avoidance tasks involving a feared stimulus are strikingly similar to the effects obtained from manipulation of other cognitive factors such as perceived self-efficacy. A number of experiments were designed to explore the relationship between self-focused attention and ffilxiety. Data from the experiments demonstrate that self-attention influences a variety of cognitive variables which have been considered as central factors in anxiety. Concomitants of self-focus are increased awareness of physiological arousal and overestimation of such arousal, the identification of self-discrepancies, cognitive failures and performance deficits and the activation of physical threat concepts in memory. These factors are conceptualised as central in the negative evaluation of physiological arousal and coping resources in anxiety. Clinically anxious individuals typically have high scores in dispositional self-consciousness and body-consciousness. In patients suffering from generalised anxiety or panic disorders maladaptive self-focusing tendencies can be related to specific life stressors which render aspects of the self salient. An analysis of the ideational component of anxiety revealed three subcomponents; negative social ideation (worry about other people's reaction to the self), negative somatic ideation (worry about physical symptoms and health) and obsessional ideation (the experience of uncontrollable and repetitive thoughts) which were differentially associated with measures of dispositional self-focus. The frequency and content of an.xious w-orry is associated with specific self-focusing tendencies. It is proposed that the 'attentional style' of the individual is an important determinant of the nature and intensity of their affective response in a threatening situation. A self-attentional model of anxiety is proposed and the complex interaction between self-focus and other cognitive factors in anxiety such as appraisal of arousal and coping resources and perceived levels of self-efficacy is discussed. The model presents new directions for research and therapeutic intervention in anxiety.

Selective oxidation of allylic alcohols over highly ordered Pd/meso-Al2 O3 catalysts

Highly ordered mesoporous alumina was prepared via evaporation induced self assembly and was impregnated to afford a family of Pd/meso-Al2O3 catalysts for the aerobic selective oxidation (selox) of allylic alcohols under mild reaction conditions. CO chemisorption and XPS identify the presence of highly dispersed (0.9–2 nm) nanoparticles comprising heavily oxidised PdO surfaces, evidencing a strong palladium-alumina interaction. Surface PdO is confirmed as the catalytically active phase responsible for allylic alcohol selox, with initial rates for Pd/meso-Al2O3 far exceeding those achievable for palladium over either amorphous alumina or mesoporous silica supports. Pd/meso-Al2O3 is exceptionally active for the atom efficient selox of diverse allylic alcohols, with activity inversely proportional to alcohol mass.

Priming moral self-ambivalence heightens deliberative behaviour in self-ambivalent individuals

Background: Recent work on cognitive-behavioural models of obsessive-compulsive disorder has focused on the roles played by various aspects of self-perception. In particular, moral self-ambivalence has been found to be associated with obsessive-compulsive phenomena. Aims: In this study we used an experimental task to investigate whether artificially priming moral self-ambivalence would increase participants' deliberation on ethical problems, an index that might be analogous to obsessive-compulsive behaviour. Method: Non-clinical participants completed two online tasks designed to prime either moral self-ambivalence, general uncertainty, or neither. All participants then completed a task requiring them to consider solutions to moral dilemmas. We recorded the time participants took to respond to the dilemmas and the length of their responses; we then combined these variables to create a measure of deliberation. Results: Priming moral self-ambivalence led to increases in deliberation, but this was only significant among those participants who scored highly on a baseline measure of moral self-ambivalence. Priming general uncertainty had no significant effect upon deliberation. Conclusions: The results suggest that moral self-ambivalence may play a role in the maintenance of obsessive-compulsive behaviour. We propose that individuals who are morally self-ambivalent might respond to situations in which this ambivalence is made salient by exhibiting behaviour with obsessive-compulsive characteristics. These findings have implications for the incorporation of ideas about self-concept into theories of obsessive-compulsive disorder.