Tools for better SLM knowledge management and informed decision-making in addressing land degradation at different scales: the WOCAT–LADA–DESIRE methodology

Desertification research conventionally focuses on the problem – that is, degradation – while neglecting the appraisal of successful conservation practices. Based on the premise that Sustainable Land Management (SLM) experiences are not sufficiently or comprehensively documented, evaluated, and shared, the World Overview of Conservation Approaches and Technologies (WOCAT) initiative (www.wocat.net), in collaboration with FAO’s Land Degradation Assessment in Drylands (LADA) project (www.fao.org/nr/lada/) and the EU’s DESIRE project (http://www.desire-project.eu/), has developed standardised tools and methods for compiling and evaluating the biophysical and socio-economic knowledge available about SLM. The tools allow SLM specialists to share their knowledge and assess the impact of SLM at the local, national, and global levels. As a whole, the WOCAT–LADA–DESIRE methodology comprises tools for documenting, self-evaluating, and assessing the impact of SLM practices, as well as for knowledge sharing and decision support in the field, at the planning level, and in scaling up identified good practices. SLM depends on flexibility and responsiveness to changing complex ecological and socioeconomic causes of land degradation. The WOCAT tools are designed to reflect and capture this capacity of SLM. In order to take account of new challenges and meet emerging needs of WOCAT users, the tools are constantly further developed and adapted. Recent enhancements include tools for improved data analysis (impact and cost/benefit), cross-scale mapping, climate change adaptation and disaster risk management, and easier reporting on SLM best practices to UNCCD and other national and international partners. Moreover, WOCAT has begun to give land users a voice by backing conventional documentation with video clips straight from the field. To promote the scaling up of SLM, WOCAT works with key institutions and partners at the local and national level, for example advisory services and implementation projects. Keywords: Sustainable Land Management (SLM), knowledge management, decision-making, WOCAT–LADA–DESIRE methodology.

Inducible caspase 9 suicide gene to improve the safety of allodepleted T cells after haploidentical stem cell transplantation.

Addback of donor T cells following T cell-depleted stem cell transplantation (SCT) can accelerate immune reconstitution and be effective against relapsed malignancy. After haploidentical SCT, a high risk of graft-versus-host disease (GVHD) essentially precludes this option, unless the T cells are first depleted of alloreactive precursor cells. Even then, the risks of severe GVHD remain significant. To increase the safety of the approach and thereby permit administration of larger T cell doses, we used a suicide gene, inducible caspase 9 (iCasp9), to transduce allodepleted T cells, permitting their destruction should administration have adverse effects. We made a retroviral vector encoding iCasp9 and a selectable marker (truncated CD19). Even after allodepletion (using anti-CD25 immunotoxin), donor T cells could be efficiently transduced, expanded, and subsequently enriched by CD19 immunomagnetic selection to >90% purity. These engineered cells retained antiviral specificity and functionality, and contained a subset with regulatory phenotype and function. Activating iCasp9 with a small-molecule dimerizer rapidly produced >90% apoptosis. Although transgene expression was downregulated in quiescent T cells, iCasp9 remained an efficient suicide gene, as expression was rapidly upregulated in activated (alloreactive) T cells. We have demonstrated the clinical feasibility of this approach after haploidentical transplantation by scaling up production using clinical grade materials.

From Broadstone to Zackenberg

Ecological networks are typically complex constructions of species and their interactions. During the last decade, the study of networks has moved from static to dynamic analyses, and has attained a deeper insight into their internal structure, heterogeneity, and temporal and spatial resolution. Here, we review, discuss and suggest research lines in the study of the spatio-temporal heterogeneity of networks and their hierarchical nature. We use case study data from two well-characterized model systems (the food web in Broadstone Stream in England and the pollination network at Zackenberg in Greenland), which are complemented with additional information from other studies. We focus upon eight topics: temporal dynamic space-for-time substitutions linkage constraints habitat borders network modularity individual-based networks invasions of networks and super networks that integrate different network types. Few studies have explicitly examined temporal change in networks, and we present examples that span from daily to decadal change: a common pattern that we see is a stable core surrounded by a group of dynamic, peripheral species, which, in pollinator networks enter the web via preferential linkage to the most generalist species. To some extent, temporal and spatial scales are interchangeable (i.e. networks exhibit ‘ergodicity’) and we explore how space-for-time substitutions can be used in the study of networks. Network structure is commonly constrained by phenological uncoupling (a temporal phenomenon), abundance, body size and population structure. Some potential links are never observed, that is they are ‘forbidden’ (fully constrained) or ‘missing’ (a sampling effect), and their absence can be just as ecologically significant as their presence. Spatial habitat borders can add heterogeneity to network structure, but their importance has rarely been studied: we explore how habitat generalization can be related to other resource dimensions. Many networks are hierarchically structured, with modules forming the basic building blocks, which can result in self-similarity. Scaling down from networks of species reveals another, finer-grained level of individual-based organization, the ecological consequences of which have yet to be fully explored. The few studies of individual-based ecological networks that are available suggest the potential for large intraspecific variance and, in the case of food webs, strong size-structuring. However, such data are still scarce and more studies are required to link individual-level and species-level networks. Invasions by alien species can be tracked by following the topological ‘career’ of the invader as it establishes itself within a network, with potentially important implications for conservation biology. Finally, by scaling up to a higher level of organization, it is possible to combine different network types (e.g. food webs and mutualistic networks) to form super networks, and this new approach has yet to be integrated into mainstream ecological research. We conclude by listing a set of research topics that we see as emerging candidates for ecological network studies in the near future.

Virtual Infrastructures as a Service enabling Converged Optical Networks and Data Centres

Abstract Cloud computing service emerged as an essential component of the Enterprise {IT} infrastructure. Migration towards a full range and large-scale convergence of Cloud and network services has become the current trend for addressing requirements of the Cloud environment. Our approach takes the infrastructure as a service paradigm to build converged virtual infrastructures, which allow offering tailored performance and enable multi-tenancy over a common physical infrastructure. Thanks to virtualization, new exploitation activities of the physical infrastructures may arise for both transport network and Data Centres services. This approach makes network and Data Centres’ resources dedicated to Cloud Computing to converge on the same flexible and scalable level. The work presented here is based on the automation of the virtual infrastructure provisioning service. On top of the virtual infrastructures, a coordinated operation and control of the different resources is performed with the objective of automatically tailoring connectivity services to the Cloud service dynamics. Furthermore, in order to support elasticity of the Cloud services through the optical network, dynamic re-planning features have been provided to the virtual infrastructure service, which allows scaling up or down existing virtual infrastructures to optimize resource utilisation and dynamically adapt to users’ demands. Thus, the dynamic re-planning of the service becomes key component for the coordination of Cloud and optical network resource in an optimal way in terms of resource utilisation. The presented work is complemented with a use case of the virtual infrastructure service being adopted in a distributed Enterprise Information System, that scales up and down as a function of the application requests.

Threat of alveolar echinococcosis to public health - a challenge for Europe

Alveolar echinococcosis (AE) is a neglected 'malignant' parasitic disease. The European endemic area of Echinococcus multilocularis in foxes is larger than previously anticipated, and there is new evidence that both fox populations and the prevalence of E. multilocularis have increased in many areas, indicating increased pressure for infection with E. multilocularis eggs in intermediate and accidental hosts, including humans. This may result in more human AE cases within the next decades. Current numbers of both immunocompetent and immunocompromised AE patients, and the anticipated future increase, call for scaling-up research to rapidly improve the development and implementation of prevention measures, early diagnosis, and curative treatment of human AE.

Sharing evidence of sustainable land management impacts

Ensuring sustainable use of natural resources is crucial for maintaining the basis for our livelihoods. With threats from climate change, disputes over water, biodiversity loss, competing claims on land, and migration increasing worldwide, the demands for sustainable land management (SLM) practices will only increase in the future. For years already, various national and international organizations (GOs, NGOs, donors, research institutes, etc.) have been working on alternative forms of land management. And numerous land users worldwide – especially small farmers – have been testing, adapting, and refining new and better ways of managing land. All too often, however, the resulting SLM knowledge has not been sufficiently evaluated, documented and shared. Among other things, this has often prevented valuable SLM knowledge from being channelled into evidence-based decision-making processes. Indeed, proper knowledge management is crucial for SLM to reach its full potential. Since more than 20 years, the international WOCAT network documents and promotes SLM through its global platform. As a whole, the WOCAT methodology comprises tools for documenting, evaluating, and assessing the impact of SLM practices, as well as for knowledge sharing, analysis and use for decision support in the field, at the planning level, and in scaling up identified good practices. In early 2014, WOCAT’s growth and ongoing improvement culminated in its being officially recognized by the UNCCD as the primary recommended database for SLM best practices. Over the years, the WOCAT network confirmed that SLM helps to prevent desertification, to increase biodiversity, enhance food security and to make people less vulnerable to the effects of climate variability and change. In addi- tion, it plays an important role in mitigating climate change through improving soil organic matter and increasing vegetation cover. In-depth assessments of SLM practices from desertification sites enabled an evaluation of how SLM addresses prevalent dryland threats. The impacts mentioned most were diversified and enhanced production and better management of water and soil degradation, whether through water harvesting, improving soil moisture, or reducing runoff. Among others, favourable local-scale cost-benefit relationships of SLM practices play a crucial role in their adoption. An economic analysis from the WOCAT database showed that land users perceive a large majority of the technologies as having benefits that outweigh costs in the long term. The high investment costs associated with some practices may constitute a barrier to adoption, however, where appropriate, short-term support for land users can help to promote these practices. The increased global concerns on climate change, disaster risks and food security redirect attention to, and trigger more funds for SLM. To provide the necessary evidence-based rationale for investing in SLM and to reinforce expert and land users assessments of SLM impacts, more field research using inter- and transdisciplinary approaches is needed. This includes developing methods to quantify and value ecosystem services, both on-site and off-site, and assess the resilience of SLM practices, as currently aimed at within the EU FP7 projects CASCADE and RECARE.

A costing exercise of provision of prevention of HIV transmission from mother to child services in Vietnam

Objectives. This dissertation focuses on estimating the cost of providing a minimum package of prevention of mother-to-child HIV transmission (PMTCT) in Vietnam from a societal perspective and discussing the issues of scaling-up the minimum package nationwide. ^ Methods. Through collection of cost-related data of PMTCT services at 22 PMTCT sites in 5 provinces (Hanoi, Quang Ninh, Thai Nguyen, Hochiminh City, and An Giang) in Vietnam, the research investigates the item cost of each service in minimum PMTCT packages and the actual cost per PMTCT site at different organizational levels including central, provincial, and district. Next, the actual cost per site at each organizational level is standardized by adjusting for HIV prevalence rate to arrive at standardized costs per site. This study then uses the standardized costs per site to project, by different scenarios, the total cost to scale-up the PMTCT program in Vietnam. ^ Results. The cost for HIV tests, infant formula, and salary of health workers are consistently found to be the biggest expenditures in the PMTCT minimum package program across all organizational levels. Annual cost for drugs for prophylaxis treatment, operating and capital, and training costs are not substantial (less than 5% of total costs at all levels). The actual annual estimated cost for a PMTCT site at the central level is nearly VND 1.9 billion or US$ 107,650 (exchange rate US$ 1 = VND 17,500) while the annual cost for a provincial site is VND 375 million or US$ 21,400. The annual cost for a district site is VND 139 million (∼US$ 8,000). ^ The estimated total annual cost to roll out the PMTCT minimum package to the 5 studied provinces is approximately US$ 1.1 million. If the PMTCT program is to be scaled-up to 14 provinces until 2008 and up to 40 provinces through the end of 2010 as planned by the Ministry of Health, it would cost the health system an approximate annual amount of US$ 2.1 million and US$ 5.04 million, respectively. The annual cost for scaling-up the PMTCT minimum package nationwide is around US$ 7.6 million. Meanwhile, the total annual cost to implement PMTCT minimum packages to achieve PMTCT national targets in 2010 (providing counseling service to 90% of all pregnant women; 60% of them will receive HIV tests and 100% of HIV (+) mother and their newborn will receive prophylaxis treatment) would be US$ 6.1 million. ^ Recommendations. This study recommends: (1) the Ministry of Health of Vietnam should adjust its short-term national targets to a more feasible and achievable level given the current level of available resources; (2) a detailed budget for scaling-up the PMTCT program should be developed together with the national PMTCT action plan; (3) the PMTCT scaling-up plan developed by the Ministry of Health should focus on coverage of high prevalence population and quality of services provided rather than number of physical provinces reached; (4) exclusive breastfeeding strategy should be promoted as part of the PMTCT program; and (5) for a smooth and effective rolling out of PMTCT services nationwide, development of a national training plan and execution of this plan must precede any other initiations of the PMTCT scaling-up plan. ^

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Large-Scale smart grids as system of systems

Smart Grids are advanced power networks that introduce intelligent management, control, and operation systems to address the new challenges generated by the growing energy demand and the appearance of renewal energies. In the literature, Smart Grids are presented as an exemplar SoS: systems composed of large heterogeneous and independent systems that leverage emergent behavior from their interaction. Smart Grids are currently scaling up the electricity service to millions of customers. These Smart Grids are known as Large-Scale Smart Grids. From the experience in several projects about Large-Scale Smart Grids, this paper defines Large-Scale Smart Grids as a SoS that integrate a set of SoS and conceptualizes the properties of this SoS. In addition, the paper defines the architectural framework for deploying the software architectures of Large-Scale Smart Grid SoS.

Characterization of ICT-based business models of social enterprises

In recent years new models for organizations working on overty alleviation have emerged. One of them, the social enterprise, has attracted the attention of both academics and practitioners all over the world. Even if defined in different ways depending on the context, social enterprise has an enormous potential to generate social benefits and to promote local agency and private initiative in poverty alleviation. In this sense, it is fitting to highlight the importance of identifying the main standards that permit the characterization of diverse social enterprises, in order to understand their main specificities and guarantee value generation for low-income populations. Another crucial factor is understanding innovation as a critical factor in promoting social enterprises. A powerful tool to enhance the impact and application of this model is Information and Communication Technologies. In the 21st century,these tools allow users to find new ways of collaboration, new sustainable business models and a cost-effective way of scaling-up initiatives. This paper, a product of the collaborative research between the Universidad Politécnica de Madrid and the Universidade Federal Fluminense, examines different business models for social enterprises and the role that ICT can play in scale and impact of these initiatives

A code for direct numerical simulation of turbulent boundary layers at high Reynolds numbers in BG/P supercomputers

A new high-resolution code for the direct numerical simulation of a zero pressure gradient turbulent boundary layers over a flat plate has been developed. Its purpose is to simulate a wide range of Reynolds numbers from Reθ = 300 to 6800 while showing a linear weak scaling up to 32,768 cores in the BG/P architecture. Special attention has been paid to the generation of proper inflow boundary conditions. The results are in good agreement with existing numerical and experimental data sets.

Entrainment Effects in Turbulent Boundary Layers

Esta tesis estudia el comportamiento de la región exterior de una capa límite turbulenta sin gradientes de presiones. Se ponen a prueba dos teorías relativamente bien establecidas. La teoría de semejanza para la pared supone que en el caso de haber una pared rugosa, el fluido sólo percibe el cambio en la fricción superficial que causa, y otros efectos secundarios quedarán confinados a una zona pegada a la pared. El consenso actual es que dicha teoría es aproximadamente cierta. En el extremo exterior de la capa límite existe una región producida por la interacción entre las estructuras turbulentas y el flujo irrotacional de la corriente libre llamada interfaz turbulenta/no turbulenta. La mayoría de los resultados al respecto sugieren la presencia de fuerzas de cortadura ligeramente más intensa, lo que la hace distinta al resto del flujo turbulento. Las propiedades de esa región probablemente cambien si la velocidad de crecimiento de la capa límite aumenta, algo que puede conseguirse aumentando la fricción en la pared. La rugosidad y la ingestión de masa están entonces relacionadas, y el comportamiento local de la interfaz turbulenta/no turbulenta puede explicar el motivo por el que las capas límite sobre paredes rugosas no se comportan como en el caso de tener paredes lisas precisamente en la zona exterior. Para estudiar las capas límite a números de Reynolds lo suficientemente elevados, se ha desarrollado un nuevo código de alta resolución para la simulación numérica directa de capas límite turbulentas sin gradiente de presión. Dicho código es capaz de simular capas límite en un intervalo de números de Reynolds entre ReT = 100 — 2000 manteniendo una buena escalabilidad hasta los dos millones de hilos en superordenadores de tipo Blue Gene/Q. Se ha guardado especial atención a la generación de condiciones de contorno a la entrada correctas. Los resultados obtenidos están en concordancia con los resultados previos, tanto en el caso de simulaciones como de experimentos. La interfaz turbulenta/no turbulenta de una capa límite se ha analizado usando un valor umbral del módulo de la vorticidad. Dicho umbral se considera un parámetro para analizar cada superficie obtenida de un contorno del módulo de la vorticidad. Se han encontrado dos regímenes distintos en función del umbral escogido con propiedades opuestas, separados por una transición topológica gradual. Las características geométricas de la zona escalan con o99 cuando u^/isdgg es la unidad de vorticidad. Las propiedades del íluido relativas a la posición del contorno de vorticidad han sido analizados para una serie de umbrales utilizando el campo de distancias esféricas, que puede obtenerse con independencia de la complejidad de la superficie de referencia. Las propiedades del fluido a una distancia dada del inerfaz también dependen del umbral de vorticidad, pero tienen características parecidas con independencia del número de Reynolds. La interacción entre la turbulencia y el flujo no turbulento se restringe a una zona muy fina con un espesor del orden de la escala de Kolmogorov local. Hacia el interior del flujo turbulento las propiedades son indistinguibles del resto de la capa límite. Se ha simulado una capa límite sin gradiente de presiones con una fuerza volumétrica cerca de la pared. La el forzado ha sido diseñado para aumentar la fricción en la pared sin introducir ningún efecto geométrico obvio. La simulación consta de dos dominios, un primer dominio más pequeño y a baja resolución que se encarga de generar condiciones de contorno correctas, y un segundo dominio mayor y a alta resolución donde se aplica el forzado. El estudio de los perfiles y los coeficientes de autocorrelación sugieren que los dos casos, el liso y el forzado, no colapsan más allá de la capa logarítmica por la complejidad geométrica de la zona intermitente, y por el hecho que la distancia a la pared no es una longitud característica. Los efectos causados por la geometría de la zona intermitente pueden evitarse utilizando el interfaz como referencia, y la distancia esférica para el análisis de sus propiedades. Las propiedades condicionadas del flujo escalan con 5QQ y u/uT, las dos únicas escalas contenidas en el modelo de semejanza de pared de Townsend, consistente con estos resultados. ABSTRACT This thesis studies the characteristics of the outer region of zero-pressure-gradient turbulent boundary layers at moderate Reynolds numbers. Two relatively established theories are put to test. The wall similarity theory states that with the presence of roughness, turbulent motion is mostly affected by the additional drag caused by the roughness, and that other secondary effects are restricted to a region very close to the wall. The consensus is that this theory is valid, but only as a first approximation. At the edge of the boundary layer there is a thin layer caused by the interaction between the turbulent eddies and the irroational fluid of the free stream, called turbulent/non-turbulent interface. The bulk of results about this layer suggest the presence of some localized shear, with properties that make it distinguishable from the rest of the turbulent flow. The properties of the interface are likely to change if the rate of spread of the turbulent boundary layer is amplified, an effect that is usually achieved by increasing the drag. Roughness and entrainment are therefore linked, and the local features of the turbulent/non-turbulent interface may explain the reason why rough-wall boundary layers deviate from the wall similarity theory precisely far from the wall. To study boundary layers at a higher Reynolds number, a new high-resolution code for the direct numerical simulation of a zero pressure gradient turbulent boundary layers over a flat plate has been developed. This code is able to simulate a wide range of Reynolds numbers from ReT =100 to 2000 while showing a linear weak scaling up to around two million threads in the BG/Q architecture. Special attention has been paid to the generation of proper inflow boundary conditions. The results are in good agreement with existing numerical and experimental data sets. The turbulent/non-turbulent interface of a boundary layer is analyzed by thresholding the vorticity magnitude field. The value of the threshold is considered a parameter in the analysis of the surfaces obtained from isocontours of the vorticity magnitude. Two different regimes for the surface can be distinguished depending on the threshold, with a gradual topological transition across which its geometrical properties change significantly. The width of the transition scales well with oQg when u^/udgg is used as a unit of vorticity. The properties of the flow relative to the position of the vorticity magnitude isocontour are analyzed within the same range of thresholds, using the ball distance field, which can be obtained regardless of the size of the domain and complexity of the interface. The properties of the flow at a given distance to the interface also depend on the threshold, but they are similar regardless of the Reynolds number. The interaction between the turbulent and the non-turbulent flow occurs in a thin layer with a thickness that scales with the Kolmogorov length. Deeper into the turbulent side, the properties are undistinguishable from the rest of the turbulent flow. A zero-pressure-gradient turbulent boundary layer with a volumetric near-wall forcing has been simulated. The forcing has been designed to increase the wall friction without introducing any obvious geometrical effect. The actual simulation is split in two domains, a smaller one in charge of the generation of correct inflow boundary conditions, and a second and larger one where the forcing is applied. The study of the one-point and twopoint statistics suggest that the forced and the smooth cases do not collapse beyond the logarithmic layer may be caused by the geometrical complexity of the intermittent region, and by the fact that the scaling with the wall-normal coordinate is no longer present. The geometrical effects can be avoided using the turbulent/non-turbulent interface as a reference frame, and the minimum distance respect to it. The conditional analysis of the vorticity field with the alternative reference frame recovers the scaling with 5QQ and v¡uT already present in the logarithmic layer, the only two length-scales allowed if Townsend’s wall similarity hypothesis is valid.

Endosperm balance number manipulation for direct in vivo germplasm introgression to potato from a sexually isolated relative (Solanum commersonii Dun.)

Diploid (2n = 2x = 24) Solanum species with endosperm balance number (EBN) = 1 are sexually isolated from diploid 2EBN species and both tetraploid (2n = 4x = 48, 4EBN) and haploid (2n = 2x = 24, 2EBN) S. tuberosum Group Tuberosum. To sexually overcome these crossing barriers in the diploid species S. commersonii (1EBN), the manipulation of the EBN was accomplished by scaling up and down ploidy levels. Triploid F1 hybrids between an in vitro-doubled clone of S. commersonii (2n = 4x = 48, 2EBN) and diploid 2EBN clones were successfully used in 3x × 4x crosses with S. tuberosum Group Tuberosum, resulting in pentaploid/near pentaploid BC1 progenies. This provided evidence of 2n (3x) egg formation in the triploid female parents. Two selected BC1 pentaploid hybrids were successfully backcrossed both as male and as female parents with S. tuberosum Group Tuberosum. The somatic chromosome number varied greatly among the resulting BC2 progenies, which included hyperaneuploids, but also a number (4.8%) of 48-chromosome plants. The introgression of S. commersonii genomes was confirmed by the presence of S. commersonii-specific randomly amplified polymorphic DNA markers in the BC2 population analyzed. The results clearly demonstrate the feasibility of germplasm introgression from sexually isolated diploid 1EBN species into the 4x (4EBN) gene pool of the cultivated potato using sexual hybridization. Based on the amount and type of genetic variation generated, cumbersomeness, general applicability, costs, and other factors, it would be interesting to compare the approach reported here with other in vitro or in vivo, direct or indirect, approaches previously reported.

Antiretroviral Treatment as Prevention in African HIV-1 Serodiscordant Couples: Understanding the Challenges and Opportunities

Thesis (Ph.D.)--University of Washington, 2016-06