Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip

Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for multi media communication applications. The heterogeneous nature of application specific on-chip cores along with the specific communication requirements among the cores calls for the design of application-specific NoCs for improved performance in terms of communication energy, latency, and throughput. In this work, we propose a methodology for the design of customized irregular networks-on-chip. The proposed method exploits a priori knowledge of the applications communication characteristic to generate an optimized network topology and corresponding routing tables.

Symmetry in Scalar Field Topology

Study of symmetric or repeating patterns in scalar fields is important in scientific data analysis because it gives deep insights into the properties of the underlying phenomenon. Though geometric symmetry has been well studied within areas like shape processing, identifying symmetry in scalar fields has remained largely unexplored due to the high computational cost of the associated algorithms. We propose a computationally efficient algorithm for detecting symmetric patterns in a scalar field distribution by analysing the topology of level sets of the scalar field. Our algorithm computes the contour tree of a given scalar field and identifies subtrees that are similar. We define a robust similarity measure for comparing subtrees of the contour tree and use it to group similar subtrees together. Regions of the domain corresponding to subtrees that belong to a common group are extracted and reported to be symmetric. Identifying symmetry in scalar fields finds applications in visualization, data exploration, and feature detection. We describe two applications in detail: symmetry-aware transfer function design and symmetry-aware isosurface extraction.

Topology Optimization of Micromachined Structures with Surface Micromachining Manufacturing Constraints

Topology optimization methods have been shown to have extensive application in the design of microsystems. However, their utility in practical situations is restricted to predominantly planar configurations due to the limitations of most microfabrication techniques in realizing structures with arbitrary topologies in the direction perpendicular to the substrate. This study addresses the problem of synthesizing optimal topologies in the out-of-plane direction while obeying the constraints imposed by surface micromachining. A new formulation that achieves this by defining a design space that implicitly obeys the manufacturing constraints with a continuous design parameterization is presented in this paper. This is in contrast to including manufacturing cost in the objective function or constraints. The resulting solutions of the new formulation obtained with gradient-based optimization directly provide the photolithographic mask layouts. Two examples that illustrate the approach for the case of stiff structures are included.

Topology Optimization of Electrostatically Actuated Micromechanical Structures with Accurate Electrostatic Modeling of the Interpolated Material Model

In this paper, we present a novel formulation for performing topology optimization of electrostatically actuated constrained elastic structures. We propose a new electrostatic-elastic formulation that uses the leaky capacitor model and material interpolation to define the material state at every point of a given design domain continuously between conductor and void states. The new formulation accurately captures the physical behavior when the material in between a conductor and a void is present during the iterative process of topology optimization. The method then uses the optimality criteria method to solve the optimization problem by iteratively pushing the state of the domain towards that of a conductor or a void in the appropriate regions. We present examples to illustrate the ability of the method in creating the stiffest structure under electrostatic force for different boundary conditions.

On the cut‐on frequencies of a large round duct with azimuthal as well as radial partitions

This letter deals with a three‐dimensional analysis of circular sectors and annular segments resulting from the partitioning of a round (cylindrical) duct for use in an active noise control system. The relevant frequency equations are derived for stationary medium and solved numerically to arrive at the cut‐on frequencies of the first few modes. The resultant table indicates among other things that azimuthal partitioning does not raise the cutoff frequency (the smallest cut‐on frequency) beyond a particular value, and that radial partitioning is counterproductive in that respect.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Design of conjugate, conjoined shapes and tilings using topology optimization

We present a method for obtaining conjugate, conjoined shapes and tilings in the context of the design of structures using topology optimization. Optimal material distribution is achieved in topology optimization by setting up a selection field in the design domain to determine the presence/absence of material there. We generalize this approach in this paper by presenting a paradigm in which the material left out by the selection field is also utilised. We obtain conjugate shapes when the region chosen and the region left-out are solutions for two problems, each with a different functionality. On the other hand, if the left-out region is connected to the selected region in some pre-determined fashion for achieving a single functionality, then we get conjoined shapes. The utilization of the left-out material, gives the notion of material economy in both cases. Thus, material wastage is avoided in the practical realization of these designs using many manufacturing techniques. This is in contrast to the wastage of left-out material during manufacture of traditional topology-optimized designs. We illustrate such shapes in the case of stiff structures and compliant mechanisms. When such designs are suitably made on domains of the unit cell of a tiling, this leads to the formation of new tilings which are functionally useful. Such shapes are not only useful for their functionality and economy of material and manufacturing, but also for their aesthetic value.