Laminar to turbulent flow transition measurements using an array of SOI-CMOS MEMS wall shear stress sensors

The successful utilization of an array of silicon on insulator complementary metal oxide semiconductor (SOICMOS) micro thermal shear stress sensors for flow measurements at macro-scale is demonstrated. The sensors use CMOS aluminum metallization as the sensing material and are embedded in low thermal conductivity silicon oxide membranes. They have been fabricated using a commercial 1 μm SOI-CMOS process and a post-CMOS DRIE back etch. The sensors with two different sizes were evaluated. The small sensors (18.5 ×18.5 μm2 sensing area on 266 × 266 μm2 oxide membrane) have an ultra low power (100 °C temperature rise at 6mW) and a small time constant of only 5.46 μs which corresponds to a cut-off frequency of 122 kHz. The large sensors (130 × 130 μm2 sensing area on 500 × 500 μm2 membrane) have a time constant of 9.82 μs (cut-off frequency of 67.9 kHz). The sensors' performance has proven to be robust under transonic and supersonic flow conditions. Also, they have successfully identified laminar, separated, transitional and turbulent boundary layers in a low speed flow. © 2008 IEEE.

Floating-body SOI memory: Concepts, physics and challenges

We present an overview of the single-transistor memory cells (lT-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling. ©The Electrochemical Society.

Thermal characterization of SOI CMOS micro hot-plate gas sensors

This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

A high temperature SOI CMOS NO2 sensor

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors. © 2011 American Institute of Physics.

Design and optimization of a 250nm SOI LDMOSFET

This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

High temperature robust SOI ethanol sensor

In this paper we present a robust SOI-CMOS ethanol sensor based on a tungsten-doped lanthanum iron oxide sensing material. The device shows response to gas, has low power consumption, good uniformity, high temperature stability and can be manufactured at low cost and with integrated circuitry. The platform is a tungsten-based CMOS micro-hotplate that has been shown to be stable for over two thousand hours at a high temperature (600°C) in a form of accelerated life test. The tungsten-doped lanthanum iron oxide was deposited on the micro-hotplate as a slurry with terpineol using a syringe, dried and annealed. Preliminary gas testing was done and the material shows response to ethanol vapour. These results are promising and we believe that this combination of a robust CMOS micro-hotplate and a good sensing material can form the basis for a commercial CMOS gas sensor. © 2011 Published by Elsevier Ltd.

Zinc oxide nanowire based hydrogen sensor on SOI CMOS platform

Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

Compact three-dimensional silicon termination solutions for high voltage SOI SuperJunction

This paper demonstrates and discusses novel "three dimensional" silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations. © 2012 IEEE.