Studies of Design and Assembly Defects on Integrated and Modular Architectures

It is known that despite companies’ efforts to improve the quality of their products, design and assembly defects results in large repair costs both in terms of repair and providing feedback to the origin of the defect. The purpose of this paper is to study these types of defects and the defect rates in design and assembly. The paper presents a web based questionnaire answered by 29 companies. The result shows that the defect rate (defects per product) spanned from 0.01 to 10. Also, design and assembly defects covered 46%, 23% respectively, of all occurred defects. A case study is also presented, performed at a company who recently implemented a modular architecture. In this company, defects from 5 700 integrated product architectures are compared with defects from 431 modular architectures. The average defect rate increased by 21.5% – from 0.65 to 0.79 – when a more modular architecture has been implemented. Furthermore, the study showed that the assembly defects have decreased while the design defects increased. The results presented in this paper will also support the development of the MPV (Module Property Verification) method which is briefly described.

Module property verification : A method to plan and perform quality verifications in modular architectures

Modular product architectures have generated numerous benefits for companies in terms of cost, lead-time and quality. The defined interfaces and the module’s properties decrease the effort to develop new product variants, and provide an opportunity to perform parallel tasks in design, manufacturing and assembly. The background of this thesis is that companies perform verifications (tests, inspections and controls) of products late, when most of the parts have been assembled. This extends the lead-time to delivery and ruins benefits from a modular product architecture; specifically when the verifications are extensive and the frequency of detected defects is high. Due to the number of product variants obtained from the modular product architecture, verifications must handle a wide range of equipment, instructions and goal values to ensure that high quality products can be delivered. As a result, the total benefits from a modular product architecture are difficult to achieve. This thesis describes a method for planning and performing verifications within a modular product architecture. The method supports companies by utilizing the defined modules for verifications already at module level, so called MPV (Module Property Verification). With MPV, defects are detected at an earlier point, compared to verification of a complete product, and the number of verifications is decreased. The MPV method is built up of three phases. In Phase A, candidate modules are evaluated on the basis of costs and lead-time of the verifications and the repair of defects. An MPV-index is obtained which quantifies the module and indicates if the module should be verified at product level or by MPV. In Phase B, the interface interaction between the modules is evaluated, as well as the distribution of properties among the modules. The purpose is to evaluate the extent to which supplementary verifications at product level is needed. Phase C supports a selection of the final verification strategy. The cost and lead-time for the supplementary verifications are considered together with the results from Phase A and B. The MPV method is based on a set of qualitative and quantitative measures and tools which provide an overview and support the achievement of cost and time efficient company specific verifications. A practical application in industry shows how the MPV method can be used, and the subsequent benefits

Transparent Fault Tolerance for Web Services based Architectures

Service-based architectures enable the development of new classes of Grid and distributed applications. One of the main capabilities provided by such systems is the dynamic and flexible integration of services, according to which services are allowed to be a part of more than one distributed system and simultaneously serve different applications. This increased flexibility in system composition makes it difficult to address classical distributed system issues such as fault-tolerance. While it is relatively easy to make an individual service fault-tolerant, improving fault-tolerance of services collaborating in multiple application scenarios is a challenging task. In this paper, we look at the issue of developing fault-tolerant service-based distributed systems, and propose an infrastructure to implement fault tolerance capabilities transparent to services.

Describing Web Service Architectures through Design-by-Contract

Architectural description languages (ADLs) are used to specify a high-level, compositional view of a software application, specifying how a system is to be composed from coarse-grain components. ADLs usually come equipped with a formal dynamic semantics, facilitating specification and analysis of distributed and event-based systems. In this paper, we describe the TrustME, an ADL framework that provides both a process and a structural view of web service-based systems. We use Petri-net descriptions to give a dynamic view of business workflow for web service collaboration. We adapt the approach of Schmidt to define a form of Meyer's design-by-contract for configuring workflow architectures. This serves as a configuration-level means of constructing safer, more robust systems.

Trust-By-Contract: Modelling, Analysing and Predicting Behaviour in Software Architectures

Architecture description languages (ADLs) are used to specify high-level, compositional views of a software application. ADL research focuses on software composed of prefabricated parts, so-called software components. ADLs usually come equipped with rigorous state-transition style semantics, facilitating verification and analysis of specifications. Consequently, ADLs are well suited to configuring distributed and event-based systems. However, additional expressive power is required for the description of enterprise software architectures – in particular, those built upon newer middleware, such as implementations of Java’s EJB specification, or Microsoft’s COM+/.NET. The enterprise requires distributed software solutions that are scalable, business-oriented and mission-critical. We can make progress toward attaining these qualities at various stages of the software development process. In particular, progress at the architectural level can be leveraged through use of an ADL that incorporates trust and dependability analysis. Also, current industry approaches to enterprise development do not address several important architectural design issues. The TrustME ADL is designed to meet these requirements, through combining approaches to software architecture specification with rigorous design-by-contract ideas. In this paper, we focus on several aspects of TrustME that facilitate specification and analysis of middleware-based architectures for trusted enterprise computing systems.

Dynamically Adapting BDI Agent Architectures based on High-level User Specifications

Users are facing an increasing challenge of managing information and being available anytime anywhere, as the web exponentially grows. As a consequence, assisting them in their routine tasks has become a relevant issue to be addressed. In this paper, we introduce a software framework that supports the development of Personal Assistance Software (PAS). It relies on the idea of exposing a high level user model in order to increase user trust in the task delegation process as well as empowering them to manage it. The framework provides a synchronization mechanism that is responsible for dynamically adapting an underlying BDI agent-based running implementation in order to keep this high-level view of user customizations consistent with it.

A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip

The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

Teste da rede de interconexões de field programmable analog arrays

Os dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays), apesar de ainda não terem a mesma popularidade de seus pares digitais (FPGAs, do inglês, Field Programmable Gate Arrays), possuem uma gama de aplicações bastante ampla, que vai desde o condicionamento de sinais em sistemas de instrumentação, até o processamento de sinais de radiofreqüência (RF) em telecomunicações. Porém, ao mesmo tempo em que os FPAAs trouxeram um impressionante ganho na agilidade de concepção de circuitos analógicos, também trouxeram um conjunto de novos problemas relativos ao teste deste tipo de dispositivo. Os FPAAs podem ser divididos em duas partes fundamentais: seus blocos programáveis básicos (CABs, do inglês, Configurable Analog Blocks) e sua rede de interconexões. A rede de interconexões, por sua vez, pode ser dividida em duas partes: interconexões internas (locais e globais entre CABs) e interconexões externas (envolvendo células de I/O). Todas estas partes apresentam características estruturais e funcionais distintas, de forma que devem ser testadas separadamente, pois necessitam que se considerem modelos de falhas, configurações e estímulos de teste específicos para assegurar uma boa taxa de detecção de defeitos. Como trabalhos anteriores já estudaram o teste dos CABs, o foco desta dissertação está direcionado ao desenvolvimento de metodologias que se propõem a testar a rede de interconexões de FPAAs. Apesar das várias diferenças entre as redes de interconexões de FPGAs e FPAAs, muitas também são as semelhanças entre elas, sendo, portanto, indiscutível que o ponto de partida deste trabalho tenha que ser o estudo das muitas técnicas propostas para o teste de interconexões em FPGAs, para posterior adaptação ao caso dos FPAAs. Além disto, embora o seu foco não recaia sobre o teste de CABs, pretende-se utilizá-los como recursos internos do dispositivo passíveis de gerar sinais e analisar respostas de teste, propondo uma abordagem de auto-teste integrado de interconexões que reduza o custo relativo ao equipamento externo de teste. Eventualmente, estes mesmos recursos poderão também ser utilizados para diagnóstico das partes defeituosas. Neste trabalho, utiliza-se como veículo de experimentação um dispositivo específico (Anadigm AN10E40), mas pretende-se que as metodologias de teste propostas sejam abrangentes e possam ser facilmente adaptadas a outros FPAAs comerciais que apresentem redes de interconexão semelhantes.