A new method of interfacing battery/supercapacitor energy storage systems for distributed energy sources

Battery-supercapacitor hybrid energy storage systems can achieve better power and energy performances compared to their individual use. These hybrid systems require separate dc-dc converters, or at least one dc-dc converter for the supercapacitor bank, to connect them to the dc-link of the grid connecting inverter. However, the use of such dc-dc converters introduces additional cost and power losses. Therefore, the possibility of direct connection of energy storage systems, to the dc-link of a diode clamped 3-level inverter is investigated in this paper. Even though the proposed topology does not use dc-dc converters, a vector selection method is proposed to produce a similar control flexibility that is found in the separate dc-dc converter topology. The major issue with the proposed system is the imminent imbalance of the neutral point potential. A PWM technique with modified carriers is used to solve this problem. Simulations are carried out using MATLAB/SIMULINK to verify the efficacy of the proposed system.

On the design of power buffer and its applications

A power electronics-based buffer is examined in which through control of its PWM converters, the buffer-load combination is driven to operate under either constant power or constant impedance modes. A battery, incorporated within the buffer, provides the energy storage facility to facilitate the necessary power flow control. Real power demand from upstream supply is regulated under fault condition, and the possibility of voltage or network instability is reduced. The proposed buffer is also applied to a wind farm. It is shown that the buffer stabilizes the power contribution from the farm. Based on a battery cost-benefit analysis, a method is developed to determine the optimal level of the power supplied from the wind farm and the corresponding capacity of the battery storage system.

Double star chopper cell converter for battery electric vehicles with inter-module SoC balancing and fault tolerant control

A modularized battery system with Double Star Chopper Cell (DSCC) based modular multilevel converter is proposed for a battery operated electric vehicle (EV). A design concept for the modularized battery micro-packs for DSCC is described. Multidimensional pulse width modulation (MD-PWM) with integrated inter-module SoC balancing and fault tolerant control is proposed and explained. The DSCC can be operated either as an inverter to drive the EV motor or as a synchronous rectifier connected to external three phase power supply equipment for charging the battery micro-packs. The methods of operation as inverter and synchronous rectifier with integrated inter-module SoC balancing and fault tolerant control are discussed. The proposed system operation as inverter and synchronous rectifier are verified through simulations and the results are presented.

HFL PV micro-inverter with front-end current-fed converter and half-wave cycloconverter

A high-frequency-link micro inverter is proposed with a front-end dual inductor push-pull converter and a grid-connected half-wave cycloconverter. Pulse width modulation is used to control the front-end converter and phase shift modulation is used at the back-end converter to obtain grid synchronized output current. A series resonant circuit and high-frequency transformer are used to interface the front-end and the back-end converters. The operation of the proposed micro-inverter in grid-connected mode is validated using MATLAB/Simpower simulation. Experimental results are provided to further validate the operation.

A DC-link Capacitor Voltage Balancing with CMV Elimination using only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control., using only inverter switching state redundancies. The proposed power circuit gives a simple power bits structure.

A Multilevel Inverter with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor Drive

This paper proposes a multilevel inverter which produces hexagonal voltage space vector structure in lower modulation region and a 12-sided polygonal space vector structure in the over-modulation region. Normal conventional multilevel inverter produces 6n +/- 1 (n=odd) harmonics in the phase voltage during over-modulation and in the extreme square wave mode operation. However, this inverter produces a 12-sided polygonal space vector location leading to the elimination of 6n 1 (n=odd) harmonics in over-modulation region extending to a final 12-step mode operation. The inverter consists of three conventional cascaded two level inverters with asymmetric dc bus voltages. The switching frequency of individual inverters is kept low throughout the modulation index. In the low speed region, hexagonal space phasor based PWM scheme and in the higher modulation region, 12-sided polygonal voltage space vector structure is used. Experimental results presented in this paper shows that the proposed converter is suitable for high power applications because of low harmonic distortion and low switching losses.

The effects of salivary gland extracts from Boophilus microplus ticks on mitogen-stimulated bovine lymphocytes

The effect of salivary gland extract (SGE) from the tick Boophilus microplus was examined in mitogen-stimulated lymphocytes in vitro. SGE was added to lymphocytes of seven cattle together with the mitogens concanavalin A (ConA), phytohaemagglutinin (PHA) and pokeweed mitogen (PWM). Semi-purified B cells from another seven cattle were stimulated with the mitogen lipopolysaccharide (LPS). PHA and ConA stimulated proliferation of lymphocytes to the same extent, but the inhibition due to SGE of Boophilus microplus on the proliferative response stimulated by PHA (39.0% ± 9.3%) was less than the inhibition of proliferative response stimulated by ConA (75.4% ± 6.9%). In contrast, SGE of B. microplus stimulated the proliferation of B cells in the presence of LPS in a dose-dependent manner. Enhanced stimulation of B cells by SGE at >4 μg in culture was greater than twice that observed when B cells were stimulated by LPS alone. SGE does not have a direct suppressive effect on bovine B cell proliferation; however, in vivo the effectiveness of B cell responses might be influenced by other immune factors, such as cytokine profiles.

A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-Level Inverter for The Full Modulation Range

A switched DC voltage three level NPC is proposed in this paper to eliminate capacitor balancing problems in conventional three-level Neutral Point Clamped (NPC) inverter. The proposed configuration requires only one DC link with a voltage V-dc/2, where V-dc is the DC link voltage in a onventional NPC inverter. To get rated DC link voltage (V-dc), the voltage source is alternately onnected in parallel to one of the two series capacitors using two switches and two diodes with device voltage rating of V-dc/2. The frequency at which the voltage source is switched is independent and will not affect the operation of NPC inverter. The switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two level inverter in lower modulation range, thereby increases the reliability of the drive system. A space vector based PWM scheme is used to verify this proposed topology.

Protection and Switching-Aid Networks for Transistor Bridge Inverters

The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

Switching period randomisation for multilevel converter modulation

The spectral energy associated with the carrier and sidebands of naturally sampled carrier based PWM can be spread by randomising the carrier (switch) half-period Tc = 1/2fc. So long as the switch duty cycle each period still correctly reflects the value of the modulating fundamental waveform as sampled during that switch period, then the fundamental component will remain undistorted. Natural sampling will ensure this occurs. Carrier based PWM can be extended to (m+1) level multilevel converter waveform generation by creating m triangular carriers, each with an equal 2*pi/m phase displacement. Alternatively the carrier disposition strategy calls for m amplitude displaced triangular carriers, each of amplitude 1/m and frequency mfc. Randomising these carrier sub-periods T0> = 1/2mfc is shown to generate (m+ 1) level PWM waveforms where the first (m-1) carrier groups are cancelled, while the remaining carrier and sidebands at multiples of mfc are spectrally spread. Numerous five level simulation and experimentally gathered randomised PWM waveforms are presented, showing the effects of the variation of the degree of randomisation, modulation depth and pulse number.

Phase accumulated carrier pulse width modulation

An alternative approach to digital PWM generation uses an accumulator rather than a counter to generate the carrier. This offers several advantages. The resolution and gain of the pulse width modulator remain constant regardless of the module clock frequency and PWM output frequency. The PWM resolution also becomes fixed at the register width. Even at high PWM frequencies, the resolution remains high when averaged over a number of PWM cycles. An inherent dithering of the PWM waveform introduced over successive cycles blurs the switching spectra without distorting the modulating waveform. The technique also lends itself to easily generating several phase shifted PWM waveforms suitable for multilevel converter modulation. Several example waveforms generated using both simulation and FPGA hardware are presented.

Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters

A novel dodecagonal space vector structure for induction motor drive is presented in this paper. It consists of two dodecagons, with the radius of the outer one twice the inner one. Compared to existing dodecagonal space vector structures, to achieve the same PWM output voltage quality, the proposed topology lowers the switching frequency of the inverters and reduces the device ratings to half. At the same time, other benefits obtained from existing dodecagonal space vector structure are retained here. This includes the extension of the linear modulation range and elimination of all 6+/-1 harmonics (n=odd) from the phase voltage. The proposed structure is realized by feeding an open-end winding induction motor with two conventional three level inverters. A detailed calculation of the PWM timings for switching the space vector points is also presented. Simulation and experimental results indicate the possible application of the proposed idea for high power drives.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulationn range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drivesystem. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for Reduced Harmonic Distortion and Switching Loss

Novel switching sequences can be employed in spacevector-based pulsewidth modulation (PWM) of voltage source inverters. Differentswitching sequences are evaluated and compared in terms of inverter switching loss. A hybrid PWM technique named minimum switching loss PWM is proposed, which reduces the inverter switching loss compared to conventional space vector PWM (CSVPWM) and discontinuous PWM techniques at a given average switching frequency. Further, four space-vector-based hybrid PWM techniques are proposed that reduce line current distortion as well as switching loss in motor drives, compared to CSVPWM. Theoretical and experimental results are presented.