Optimised two-temperature growth of GaAs nanowire s by metalorganic chemical vapour deposition

We report a two-temperature procedure for the growth of GaAs nanowires by metalorganic chemical vapour deposition. An initial high temperature step affords effective nucleation and promotes epitaxial growth of straight (111)B-oriented nanowires. Lower temperatures are employed subsequently, to minimise nanowire tapering during growth. © 2006 IEEE.

Catalyst composition and impurity-dependent kinetics of nanowire heteroepitaxy.

The mechanisms and kinetics of axial Ge-Si nanowire heteroepitaxial growth based on the tailoring of the Au catalyst composition via Ga alloying are studied by environmental transmission electron microscopy combined with systematic ex situ CVD calibrations. The morphology of the Ge-Si heterojunction, in particular, the extent of a local, asymmetric increase in nanowire diameter, is found to depend on the Ga composition of the catalyst, on the TMGa precursor exposure temperature, and on the presence of dopants. To rationalize the findings, a general nucleation-based model for nanowire heteroepitaxy is established which is anticipated to be relevant to a wide range of material systems and device-enabling heterostructures.

Direct observation of charge-carrier heating at WZ-ZB InP nanowire heterojunctions.

We have investigated the dynamics of hot charge carriers in InP nanowire ensembles containing a range of densities of zinc-blende inclusions along the otherwise wurtzite nanowires. From time-dependent photoluminescence spectra, we extract the temperature of the charge carriers as a function of time after nonresonant excitation. We find that charge-carrier temperature initially decreases rapidly with time in accordance with efficient heat transfer to lattice vibrations. However, cooling rates are subsequently slowed and are significantly lower for nanowires containing a higher density of stacking faults. We conclude that the transfer of charges across the type II interface is followed by release of additional energy to the lattice, which raises the phonon bath temperature above equilibrium and impedes the carrier cooling occurring through interaction with such phonons. These results demonstrate that type II heterointerfaces in semiconductor nanowires can sustain a hot charge-carrier distribution over an extended time period. In photovoltaic applications, such heterointerfaces may hence both reduce recombination rates and limit energy losses by allowing hot-carrier harvesting.

Electronic comparison of InAs wurtzite and zincblende phases using nanowire transistors

We compare the electronic characteristics of nanowire field-effect transistors made using single pure wurtzite and pure zincblende InAs nanowires grown from identical catalyst particles. We compare the transfer characteristics and field-effect mobility versus temperature for these devices to better understand how differences in InAs phase govern the electronic properties of nanowire transistors. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance nanowire oxide photo-thin film transistor.

A gate-modulated nanowire oxide photosensor is fabricated by electron-beam lithography and conventional dry etch processing.. The device characteristics are good, including endurance of up to 10(6) test cycles, and gate-pulse excitation is used to remove persistent photoconductivity. The viability of nanowire oxide phototransistors for high speed and high resolution applications is demonstrated, thus potentially expanding the scope of exploitation of touch-free interactive displays.

Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap, which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices. © 2013 American Chemical Society.

Twin plane re-entrant mechanism for catalytic nanowire growth.

A twin-plane based nanowire growth mechanism is established using Au catalyzed Ge nanowire growth as a model system. Video-rate lattice-resolved environmental transmission electron microscopy shows a convex, V-shaped liquid catalyst-nanowire growth interface for a ⟨112⟩ growth direction that is composed of two Ge {111} planes that meet at a twin boundary. Unlike bulk crystals, the nanowire geometry allows steady-state growth with a single twin boundary at the nanowire center. We suggest that the nucleation barrier at the twin-plane re-entrant groove is effectively reduced by the line energy, and hence the twin acts as a preferential nucleation site that dictates the lateral step flow cycle which constitutes nanowire growth.

Fast, sensitive and low-noise nanowire and graphene field effect transistors for room-temperature detection of Terahertz quantum cascade laser emission

Antenna-coupled field effect transistors have been developed as plasma-wave THz detectors in both InAs nanowire and graphene channel materials. Room temperature operation has been achieved up to 3 THz, with noise equivalent power levels < 10-10 W/Hz1/2, and high-speed response already suitable for large area THz imaging applications. © 2013 IEEE.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s. © 2014 AIP Publishing LLC.

Influence of ZnS and MgO Shell on the Photoluminescence Properties of ZnO Core/Shell Nanowire

Chinese Academy of Sciences；National Science Fund for Distinguished Young Scholar 60925016；National High Technology Research and Development program of China 2009AA034101；Postdoctoral Foundation 0971050000

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Fabry-Perot microcavity modes observed in the micro-photoluminescence spectra of the single nanowire with InGaAs/GaAs heterostructure

We report on the fabrication of the nanowires with InGaAs/GaAs heterostructures on the GaAs(111) B substrate using selective-area metal organic vapor phase epitaxy. Fabry-Perot microcavity modes were observed in the nanowires with perfect end facets dispersed onto the silicon substrate and not observed in the free-standing nanowires. We find that the calculated group refractive indices only considering the material dispersion do not agree with the experimentally determined values although this method was used by some researchers. The calculated group refractive indices considering both the material dispersion and the waveguide dispersion agree with the experimentally determined values well. We also find that Fabry-Perot microcavity modes are not observable in the nanowires with the width less than about 180 nm, which is mainly caused by their poor reflectivity at the end facets due to their weak confinement to the optical field. (C) 2009 Optical Society of America

Wavelength conversion based on degenerate-four-wave-mixing with continuous-wave pumping in silicon nanowire waveguide

We present a comprehensive numerical study on the all-optical wavelength conversion based on the degenerate four-wave-mixing with continuous-wave pumping in the silicon nanowire waveguide. It is well known that the conversion efficiency and the 3-dB bandwidth can be greatly affected by the phase-matching condition. Through proper design of the waveguide cross-section, its dispersion property can be adjusted to satisfy the phase-matching condition and therefore effective wavelength conversion can be achieved in a large wavelength range. Generally, the group velocity dispersion plays a dominant role in the wavelength conversion. However, the fourth-order dispersion takes an important effect on the wavelength conversion when the group velocity dispersion is near the zero-point. Furthermore, the conversion efficiency and the 3-dB bandwidth can also be affected by the interactive length and the initial pump power. Through the numerical simulation, the optimal values for the interactive length and the initial pump power, which are functions of the propagation loss, are obtained to realize the maximum conversion efficiency. (C) 2008 Elsevier B.V. All rights reserved.

Effects of waveguide length and pump power on the efficiency of wavelength conversion in silicon nanowire waveguides

We point out the use of a wrong definition for conversion efficiency in the literature and analyze the effects of the waveguide length and pump power on conversion efficiency according to the correct definition. The existence of the locally optimal waveguide length and pump power is demonstrated theoretically and experimentally. Further analysis shows that the extremum of conversion efficiency can be achieved by global optimization of the waveguide length and pump power simultaneously, which is limited by just the linear propagation loss and the effective carrier lifetime. (C) 2009 Optical Society of America