Assembly of a high-dielectric constant thin TiOX layer directly on H-terminated semiconductor diamond

A high-dielectric constant (high-k) TiOx thin layer was fabricated on hydrogen-terminated diamond (H-diamond) surface by low temperature oxidation of a thin titanium layer in ambient air. The metallic titanium layer was deposited by sputter deposition. The dielectric constant of the resultant TiOx was calculated to be around 12. The capacitance density of the metal-oxide-semiconductor (MOS) based on the TiOx/H-diamond was as high as 0.75 µF/cm2 contributed from the high-k value and the very thin thickness of the TiOx layer. The leakage current was lower than 10-13 A at reverse biases and 10-7A at the forward bias of -2 V. The MOS field-effect transistor based on the high-k TiOx/H-diamond was demonstrated. The utilization of the high-k TiOx with a very thin thickness brought forward the features of an ideally low subthreshold swing slope of 65 mV per decade and improved drain current at low gate voltages. The advantages of the utilization high-k dielectric for diamond MOSFETs are anticipated.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Deposition of Intrinsic a-Si:H by ECR-CVD to Passivate the Crystalline Silicon Heterointerface in HIT Solar Cells

We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15-30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9- 2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100°C. In addition, we prove that the metal-oxide- semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D_it as low as 8 × 10^10 cm^2 · eV^-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

Post-CMOS compatible high-throughput fabrication of AIN-based piezoelectric microcantilevers

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

Electro-optical characterization of IC compatible microcantilevers

The aim of this work is to simulate and optically characterize the piezoelectric performance of complementary metal oxide semiconductor (CMOS) compatible microcantilevers based on aluminium nitride (AlN) and manufactured at room temperature. This study should facilitate the integration of piezoelectric micro-electro-mechanical systems (MEMS) such as microcantilevers, in CMOS technology. Besides compatibility with standard integrated circuit manufacturing procedures, low temperature processing also translates into higher throughput and, as a consequence, lower manufacturing costs. Thus, the use of the piezoelectric properties of AlN manufactured by reactive sputtering at room temperature is an important step towards the integration of this type of devices within future CMOS technology standards. To assess the reliability of our fabrication process, we have manufactured arrays of free-standing microcantilever beams of variable dimension and studied their piezoelectric performance. The characterization of the first out-of-plane modes of AlN-actuated piezoelectric microcantilevers has been carried out using two optical techniques: laser Doppler vibrometry (LDV) and white light interferometry (WLI). In order to actuate the cantilevers, a periodic chirp signal in certain frequency ranges was applied between the device electrodes. The nature of the different vibration modes detected has been studied and compared with that obtained by a finite element model based simulation (COMSOL Multiphysics), showing flexural as well as torsional modes. The correspondence between theoretical and experimental data is reasonably good, probing the viability of this high throughput and CMOS compatible fabrication process. To complete the study, X-ray diffraction as well as d33 piezoelectric coefficient measurements were also carried out.

Scanning tunneling microscope operating as a spin diode

We theoretically investigate spin-polarized transport in a system composed of a ferromagnetic scanning-tunneling-microscope (STM) tip coupled to an adsorbed atom (adatom) on a host surface. Electrons can tunnel directly from the tip to the surface or via the adatom. Since the tip is ferromagnetic and the host surface (metal or semiconductor) is nonmagnetic we obtain a spin-diode effect when the adatom is in the regime of single occupancy. This effect leads to an unpolarized current for direct bias (V > 0) and polarized current for reverse (V < 0) bias voltages, if the tip is nearby the adatom. Within the nonequilibrium Keldysh technique we analyze the interplay between the lateral displacement of the tip and the intra adatom Coulomb interaction on the spin-diode effect. As the tip moves away from the adatom the spin-diode effect vanishes and the currents become polarized for both V > 0 and V < 0. We also find an imbalance between the up and down spin populations in the adatom, which can be tuned by the tip position and the bias. Finally, due to the presence of the adsorbate on the surface, we observe spin-resolved Friedel oscillations in the current, which reflects the oscillations in the calculated local density of states (LDOS) of the subsystem surface + adatom.

A novel subwavelength plasmon-polariton optical filter based on tilted coupled structures

This work proposes a completely new approach for the design of resonant structures aiming at wavelength-filtering applications. The structure consists of a subwavelength metal-insulator-metal (MIM) waveguide presenting tilted coupled structures transversely arranged in the midpoint between the input and output ports. The cavity-like response of this device has shown that this concept can be particularly attractive for optical filter design for telecom applications. The extra degree of freedom provided by the tilting of the cavity has proved to be not only very effective on improving the quality factor of these structures, but also to be an elegant way of extending the range of applications for tuning multiple wavelengths, if necessary.

Phase diagram of the one-dimensional Holstein model of spinless fermions

The one-dimensional Holstein model of spinless fermions interacting with dispersionless phonons is studied using a new variant of the density matrix renormalization group. By examining various low-energy excitations of finite chains, the metal-insulator phase boundary is determined precisely and agrees with the predictions of strong coupling theory in the antiadiabatic regime and is consistent with renormalization group arguments in the adiabatic regime. The Luttinger liquid parameters, determined by finite-size scaling, are consistent with a Kosterlitz-Thouless transition.

Large-N solutions of the Heisenberg and Hubbard-Heisenberg models on the anisotropic triangular lattice: application to Cs2CuCl4 and to the layered organic superconductors kappa-(BEDT-TTF)(2)X (BEDT-TTF bis(ethylene-dithio)tetrathiafulvalene); X anion)

We solve the Sp(N) Heisenberg and SU(N) Hubbard-Heisenberg models on the anisotropic triangular lattice in the large-N limit. These two models may describe respectively the magnetic and electronic properties of the family of layered organic materials K-(BEDT-TTF)(2)X, The Heisenberg model is also relevant to the frustrated antiferromagnet, Cs2CuCl4. We find rich phase diagrams for each model. The Sp(N) :antiferromagnet is shown to have five different phases as a function of the size of the spin and the degree of anisotropy of the triangular lattice. The effects of fluctuations at finite N are also discussed. For parameters relevant to Cs2CuCl4 the ground state either exhibits incommensurate spin order, or is in a quantum disordered phase with deconfined spin-1/2 excitations and topological order. The SU(N) Hubbard-Heisenberg model exhibits an insulating dimer phase, an insulating box phase, a semi-metallic staggered flux phase (SFP), and a metallic uniform phase. The uniform and SFP phases exhibit a pseudogap, A metal-insulator transition occurs at intermediate values of the interaction strength.

A DC Voltage-Multiplier Circuit Working as a High-Voltage Pulse Generator

The intensive use of semiconductor devices enabled the development of a repetitive high-voltage pulse-generator topology from the dc voltage-multiplier (VM) concept. The proposed circuit is based on an odd VM-type circuit, where a number of dc capacitors share a common connection with different voltage ratings in each one, and the output voltage comes from a single capacitor. Standard VM rectifier and coupling diodes are used for charging the energy-storing capacitors, from an ac power supply, and two additional on/off semiconductors in each stage, to switch from the typical charging VM mode to a pulse mode with the dc energy-storing capacitors connected in series with the load. Results from a 2-kV experimental prototype with three stages, delivering a 10-mu s pulse with a 5-kHz repetition rate into a resistive load, are discussed. Additionally, the proposed circuit is compared against the solid-state Marx generator topology for the same peak input and output voltages.

Implementação de WDM com dispositivos semicondutores

Este trabalho utiliza uma estrutura pin empilhada, baseada numa liga de siliceto de carbono amorfo hidrogenado (a-Si:H e/ou a-SiC:H), que funciona como filtro óptico na zona visível do espectro electromagnético. Pretende-se utilizar este dispositivo para realizar a demultiplexagem de sinais ópticos e desenvolver um algoritmo que permita fazer o reconhecimento autónomo do sinal transmitido em cada canal. O objectivo desta tese visa implementar um algoritmo que permita o reconhecimento autónomo da informação transmitida por cada canal através da leitura da fotocorrente fornecida pelo dispositivo. O tema deste trabalho resulta das conclusões de trabalhos anteriores, em que este dispositivo e outros de configuração idêntica foram analisados, de forma a explorar a sua utilização na implementação da tecnologia WDM. Neste trabalho foram utilizados três canais de transmissão (Azul – 470 nm, Verde – 525 nm e Vermelho – 626 nm) e vários tipos de radiação de fundo. Foram realizadas medidas da resposta espectral e da resposta temporal da fotocorrente do dispositivo, em diferentes condições experimentais. Variou-se o comprimento de onda do canal e o comprimento de onda do fundo aplicado, mantendo-se constante a intensidade do canal e a frequência de transmissão. Os resultados obtidos permitiram aferir sobre a influência da presença da radiação de fundo e da tensão aplicada ao dispositivo, usando diferentes sequências de dados transmitidos nos vários canais. Verificou-se, que sob polarização inversa, a radiação de fundo vermelho amplifica os valores de fotocorrente do canal azul e a radiação de fundo azul amplifica o canal vermelho e verde. Para polarização directa, apenas a radiação de fundo azul amplifica os valores de fotocorrente do canal vermelho. Enquanto para ambas as polarizações, a radiação de fundo verde, não tem uma grande influência nos restantes canais. Foram implementados dois algoritmos para proceder ao reconhecimento da informação de cada canal. Na primeira abordagem usou-se a informação contida nas medidas de fotocorrente geradas pelo dispositivo sob polarização inversa e directa. Pela comparação das duas medidas desenvolveu-se e testou-se um algoritmo que permite o reconhecimento dos canais individuais. Numa segunda abordagem procedeu-se ao reconhecimento da informação de cada canal mas com aplicação de radiação de fundo, tendo-se usado a informação contida nas medidas de fotocorrente geradas pelo dispositivo sob polarização inversa sem aplicação de radiação de fundo com a informação contida nas medidas de fotocorrente geradas pelo dispositivo sob polarização inversa com aplicação de radiação de fundo. Pela comparação destas duas medidas desenvolveu-se e testou-se o segundo algoritmo que permite o reconhecimento dos canais individuais com base na aplicação de radiação de fundo.

Electrical transport properties of CuS single crystals

Electrical resistivity, transverse magnetoresistance and thermoelectric power measurements were performed on CuS high quality single crystals in the range 1.2-300 K and under fields of up to 16 T. The zero field resistivity data are well described below 55 K by a quasi-2D model, consistent with a carrier confinement at lower temperatures, before the transition to the superconducting state. The transverse magnetoresistance develops mainly below 30 K and attains values as large as 470% for a 16 T field at 5 K, this behaviour being ascribed to a band effect mechanism, with a possible magnetic field induced DOS change at the Fermi level. The transverse magnetoresistance shows no signs of saturation, following a power law with field Delta rho/rho(0) proportional to H(1.4), suggesting the existence of open orbits for carriers at the Fermi surface. The thermoelectric power shows an unusual temperature dependence, probably as a result of the complex band structure of CuS.

Sistema WDM de 4 canais

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Produção e caracterização de silício policristalino e sua aplicação a TFTS

Dissertação para obtenção do Grau de Doutor em Engenharia dos Materiais, especialidade Microelectrónica e Optoelectrónica, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia