Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Generation of High Magnetic Fields Using Thyristors

This paper describes the use of high-power thyristors in conjunction with a low-voltage supply for generating pulsed magnetic fields. A modular bank of electrolytic capacitors is charged through a programmable solid-state power supply and then rapidly discharged through a bank of thyristors into a magnetizing coil. The modular construction of capacitor banks enables the discrete control of pulse energy and time. Peak fields up to 15 telsa (150 KOe) and a half period of about 200 microseconds are generated through the discharges. Still higher fields are produced by discharging into a precooled coil ( 77°K). Measurement method for a pulsed field is described.

An ultra low power OTA with improved unity gain bandwidth product

An operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) and hybrid compensation technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair. Two separate capacitors are employed for the OTA compensation where one of them is used in a signal path and the other one in a non-signal path. The circuit is designed in the 0.18μm CMOS TSMC technology. The proposed design technique shows remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair OTAs. The Hspice simulation results show that the amplifier has a 92dB open-loop DC gain and a unity gain-bandwidth of 135kHz while operating at 0.4V supply voltage. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical and bio-implantable applications.

Efficiency analysis of an isolated high voltage gain converter operating in resonant and non-resonant mode

This paper presents an efficiency investigation of an isolated high step-up ratio dc-dc converter aimed to be used for energy processing from low-voltage high-current energy sources, like batteries, photovoltaic modules or fuel-cells. The considered converter consists of an interleaved active clamp flyback topology combined with a voltage multiplier at the transformer secondary side capable of two different operating modes, i.e. resonant and non-resonant according to the design of the output capacitors. The main goal of this paper is to compare these two operating modes from the component losses point of view with the aim of maximize the overall converter efficiency. The approach is based on losses prediction using steady-state theoretical models (designed in Mathcad environment), taking into account both conduction and switching losses. The models are compared with steady-state simulations and experimental results considering different operating modes to validate the approach. © 2012 IEEE.

Sensitivity analysis of voltage imbalance in distribution networks with rooftop PVs

A comprehensive voltage imbalance sensitivity analysis and stochastic evaluation based on the rating and location of single-phase grid-connected rooftop photovoltaic cells (PVs) in a residential low voltage distribution network are presented. The voltage imbalance at different locations along a feeder is investigated. In addition, the sensitivity analysis is performed for voltage imbalance in one feeder when PVs are installed in other feeders of the network. A stochastic evaluation based on Monte Carlo method is carried out to investigate the risk index of the non-standard voltage imbalance in the network in the presence of PVs. The network voltage imbalance characteristic based on different criteria of PV rating and location and network conditions is generalized. Improvement methods are proposed for voltage imbalance reduction and their efficacy is verified by comparing their risk index using Monte Carlo simulations.

Smart robust resources control in LV network to deal with voltage rise issue

Often voltage rise along low voltage (LV) networks limits their capacity to accommodate more renewable energy (RE) sources. This paper proposes a robust and effective approach to coordinate customers' resources and control voltage rise in LV networks, where photovoltaics (PVs) are considered as the RE sources. The proposed coordination algorithm includes both localized and distributed control strategies. The localized strategy determines the value of PV inverter active and reactive power, while the distributed strategy coordinates customers' energy storage units (ESUs). To verify the effectiveness of proposed approach, a typical residential LV network is used and simulated in the PSCAD-EMTC platform.

Distribution tap changer adjustment to improve small-scale embedded generator penetration and mitigate voltage rise

This paper addresses the voltage rise constraints that are initiated from increased renewable generation resources in low voltage distribution networks. In this paper, an approach which is able to mitigate these voltage rise constraints and allow for increased distributed generator penetration is presented. The proposed approach involves utilizing the distribution transformers static tap changer to reduce the distribution feeder voltage setpoint. The proposed approach is modeled on a generic low voltage distribution network using the PSS SINCAL© simulation software package and is also implemented in a real low voltage distribution network to verify its practicality. Results indicate that this approach can be implemented to mitigate the voltage rise constraint and increase small-scale embedded generator penetration in a high proportion of low voltage feeders while avoiding any substantial network costs.

A coordinated voltage support strategy for LV network with multiple DSTATCOMs

Voltage rise and drop are the main power quality challenges in Low Voltage (LV) network with Renewable Energy (RE) generators. This paper proposes a new voltage support strategy based on coordination of multiple Distribution Static Synchronous Compensators (DSTATCOMs) using consensus algorithm. The study focuses on LV network with PV as the RE source for customers. The proposed approach applied to a typical residential LV network and its advantages are shown comparing with other voltage control strategies.

Electrical insulation of high voltage inductor with co-axial electrode at floating voltage

Inductive fault current limiters (FCLs) have several advantages, such as significant current limitation, immediate triggering and relatively low losses. Despite these advantages, saturated core FCLs have not been commercialized due to its large size and associated high costs. A major remaining challenge is to reduce the footprint of the device. In this paper, a solution to reduce the overall footprint is proposed and discussed. In arrangements of windings on a core in reactors such as FCLs, the core is conventionally grounded. The electrical insulation distance between high voltage winding and core can be reduced if the core is left at floating potential. This paper shows the results of the investigation carried out on the insulation of such a coil-core assembly. Two experiments were conducted. In the first, the behavior of the apparatus under high voltage conditions was assessed by performing power frequency and lightning impulse tests. In the second experiment, a low voltage test was conducted during which voltages of different frequencies and pulses with varying rise times were applied. A finite element simulation was also carried out for comparison and further investigation

Improving voltage profile of residential distribution systems using rooftop PVs and Battery Energy Storage systems

Large number of rooftop Photovoltaics (PVs) have turned traditional passive networks into active networks with intermittent and bidirectional power flow. A community based distribution network grid reinforcement process is proposed to address technical challenges associated with large integration of rooftop PVs. Probabilistic estimation of intermittent PV generation is considered. Depending on the network parameters such as the R/X ratio of distribution feeder, either reactive control from PVs or coordinated control of PVs and Battery Energy Storage (BES) has been proposed. Determination of BES capacity is one of the significant outcomes from the proposed method and several factors such as variation in PV installed capacity as well as participation from community members are analyzed. The proposed approach is convenient for the community members providing them flexibility of managing their integrated PV and BES systems

Utilizing reactive capability of PV inverters and battery systems to improve voltage profile of a residential distribution feeder

Significant increase in installation of rooftop Photovoltaic (PV) in the Low-Voltage (LV) residential distribution network has resulted in over voltage problems. Moreover, increasing peak demand creates voltage dip problems and make voltage profile even worse. Utilizing the reactive power capability of PV inverter (RCPVI) can improve the voltage profile to some extent. Resistive caharcteristic (higher R/X ratio) limits the effectiveness of reactive power to provide voltage support in distribution network. Battery Energy Storage (BES), whereas, can store the excess PV generation during high solar insolation time and supply the stored energy back to the grid during peak demand. A coordinated algorithm is developed in this paper to use the reactive capability of PV inverter and BES with droop control. Proposed algorithm is capable to cater the severe voltage violation problem using RCPVI and BES. A signal flow is also mentioned in this research work to ensure smooth communication between all the equipments. Finally the developed algorithm is validated in a test distribution network.

A coaxial capacitive voltage divider for oscilloscopic recording of nanosecond high voltage pulses

A coaxial capacitance voltage divider with a ratio of 110 and a rise time much less than 2.5 ns was developed for use with a transmission line pulse generator capable of producing 100 kV rectangular pulses of 2 mu s duration. The low voltage arm of the divider is a 3 cm long tube of titania (TiO2) turned out from a cylindrical compact. The compact was made by first pressing titania powder using a suitable binder and then sintering at controlled temperatures. The tube was slipped over the terminating end of the pulse-forming cable to form the divider with the cable capacitance.

Low temperature processing and chacterization of SrBi2Nb2O9 thin films grown by pulsed laser ablation

Ex-situ grown thin films of SrBi2Nb2O9 (SBN) were deposited on platinum substrates using laser ablation technique. A low substrate-temperature-processing route was chosen to avoid any diffusion of bismuth into the Pt electrode. It was observed that the as grown films showed an oriented growth along the 'c'-axis (with zero spontaneous polarization). The as grown films were subsequently annealed to enhance crystallization. Upon annealing, these films transformed into a polycrystalline structure, and exhibited excellent ferroelectric properties. The switching was made to be possible by lowering the thickness without losing the electrically insulating behavior of the films. The hysteresis results showed an excellent square-shaped loop with results (P-r = 4 muC/cm(2) E-c = 90 kV/cm) in good agreement with the earlier reports. The films also exhibited a dielectric constant of 190 and a dissipation factor of 0.02, which showed dispersion at low frequencies. The frequency dispersion was found to obey Jonscher's universal power law relation, and was attributed to the ionic charge hopping process according to earlier reports. The de transport studies indicated an ohmic behavior in the low voltage region, while higher voltages induced a bulk space charge and resulted in non-linear current-voltage dependence.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

700V smart trench IGBT with monolithic over-voltage and over-current protecting functions

An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M 1), an avalanche diode (D av), and poly-crystalline Zener diodes (ZD) and resistor (R poly). Mix-mode transient simulations with MEDICI have proven the functionalities of the protecting circuits when the device is operating under abnormal conditions, such as Unclamped Inductive Switching (UIS) and Short Circuit (SC) condition. A Trench IGBT process is used to fabricate this device with total 11 masks including one metal mask only. The characterizations of the fabricated device exhibit the clamping capability of the avalanche diode and voltage pull-down ability of the MOSFET. © 2012 IEEE.