A current-mode based Field-Programmable Analog Array for signal processing applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Settling analysis of MOS regulated current mirrors applied to micropower D/A converters

This paper provides an insight to the trade-off between settling time and power consumption in regulated current mirrors as building parts in micropower current-switching D/A converters. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are evaluated. Raising pole frequencies in micropower circuits, while meeting consumption requirements, is basically limited by parasitic capacitances. For such cases, an alternative is to impose a twin-pole condition in which design constraints are somewhat relieved and settling slightly improved. Relationships between pole frequencies, transistor geometry and bias are established and design guidelines for regulated current mirrors founded. By placing loop-transistors in either weak or strong inversion, small (W/L) ratios are allowed and stray capacitances reduced. Simulated waveforms suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves both simulated and experimental settling performance.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

Design of a LNA and a Gilbert Cell Mixer MMICs with a GaAs PHEMT technology

The design of a Gilbert Cell Mixer and a low noise amplifier (LNA), using GaAs PHEMT technology is presented. The compatibility is shown for co-integration of both block on the same chip, to form a high performance 1.9 GHz receiver front-end. The designed LNA shows 9.23 dB gain and 2.01 dB noise figure (NF). The mixer is designed to operate at RF=1.9 GHz, LO=2.0 GHz and IF=100 MHz with a gain of 14.3 dB and single sideband noise figure (SSB NF) of 9.6 dB. The mixer presents a bandwith of 8 GHz.

A high speed 3.3V current mode CMOS comparators with 10-b resolution

This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS n-well process with area of 120μm × 105μm and operates with 3.3V(±1.65V).

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology

This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian parameters (gain, center and width) is changed with programmable current source. Results obtained with PSPICE software is showed.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

On designing linearly tunable high-Q OTA-C filters with low sensitivity

This paper discusses a design approach for a high-Q low-sensitivity OTA-C biquad bandpass section. An optimal relationship is established between transconductances defining the differenceβ - γ in the Q-factor denominator, setting the Q-sensitivity to tuning voltages around unity. A 30-MHz filter was designed based on a 0.35μn CMOS process and VDD=3.3V. A range of circuit simulation supports the theoretical analysis. Q-factor spans from 20.5 to 60, while ensuring filter stability along the tuning range. Although a Mode-operating OTA is used, the procedure can be extended to other types of transconductor.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Common architecture for discrete wavelet transform analysis and synthesis with sequential and constant processing elements

This paper adresses the problem on processing biological data such as cardiac beats, audio and ultrasonic range, calculating wavelet coefficients in real time, with processor clock running at frequency of present ASIC's and FPGA. The Paralell Filter Architecture for DWT has been improved, calculating wavelet coefficients in real time with hardware reduced to 60%. The new architecture, which also processes IDWT, is implemented with the Radix-2 or the Booth-Wallace Constant multipliers. Including series memory register banks, one integrated circuit Signal Analyzer, ultrasonic range, is presented.

Dimmable electronic ballast with high power-factor SEPIC preregulator, for multiple tubular fluorescent lamps

An electronic ballast for multiple tubular fluorescent lamps is presented in this paper. The proposed structure features high power-factor, dimming capability, and soft-switching to the semiconductor devices operated in high frequencies. A Zero-Current-Switching - Pulse-Width-Modulated (ZCS-PWM) SEPIC converter composes the rectifying stage, controlled by the instantaneous average input current technique, performing soft-commutations and high input power factor. Regarding the inverting stage, it is composed by a classical resonant Half-Bridge converter, associated to Series Parallel-Loaded Resonant (SPLR) filters. The dimming control technique employed in this Half-Bridge inverter is based on the phase-shift in the current processed through the sets of filter + lamp. In addition, experimental results are shown in order to validate the developed analysis.

Discrete wavelet transform signal analyzer

This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency of present application-specified integrated circuits and field programmable gate array. The parallel filter architecture for discrete wavelet transform (DWT) has been improved, calculating the wavelet coefficients in real time with hardware reduced up to 60%. The new architecture, which also processes inverse DWT, is implemented with the Radix-2 or the Booth-Wallace constant multipliers. One integrated circuit signal analyzer in the ultrasonic range, including series memory register banks, is presented. © 2007 IEEE.

CMOS-based active pixel for low-light-level detection: Analysis and measurements

An analysis of the active pixel sensor (APS), considering the doping profiles of the photodiode in an APS fabricated in a 0.18 μm standard CMOS technology, is presented. A simple and accurate model for the junction capacitance of the photodiode is proposed. An analytic expression for the output voltage of the APS obtained with this capacitance model is in good agreement with measurements and is more accurate than the models used previously. A different mode of operation for the APS based on the dc level of the output is suggested. This new mode has better low-light-level sensitivity than the conventional APS operating mode, and it has a slower temporal response to the change of the incident light power. At 1μW/cm2 and lower levels of light, the measured signal-to-noise ratio (SNR) of this new mode is more than 10 dB higher than the SNR of previously reported APS circuits. Also, with an output SNR of about 10 dB, the proposed dc level is capable of detecting light powers as low as 20 nW/cm2, which is about 30 times lower than the light power detected in recent reports by other groups. © 2007 IEEE.