Valokuvallistettu luonto : I. K. Inhan tuotanto luonnon merkityksellistäjänä

Photographized nature I. K. Inha s work as a signification of nature The dissertation examines, through the work of the Finnish photographer and writer I. K. Inha (formerly Konrad Into Nyström) (1865 1930), the different ways in which the signification of nature is achieved. The principal material consists of Inha s work from 1890 to 1925, from which a number of photographs and texts are considered and upon which the photographization of nature is contemplated. The dissertation addresses the issue of how nature is conceived and how the act of photographizing it can be defined. The methodical context of the study is composed of three thematic baskets that structure the material and which consist of narrations on Finnish national perception, nature conservation and understanding the world. In the first case nature is seen as the natural environment encompassing lakes, seashores, forests, and hills, which at the time were often perceived from a utilitarian viewpoint. By the photographization they generated a pictorial narrative that could be shared. The natural environment was thus turned into landscape by means of photography, following the global pictorial concepts picturesque and sublime, as well as the national canons that had been developed in literature and the visual arts. In the narrations concerning nature conservation, the photographization did not merely occur within the limits of presuppositions, but rather nature was given the opportunity to unfold itself. While the photograph was being established as a basis for supporting nature conservation or to highlight the destruction of nature at the hand of Man, an attempt was made to represent subjects that were difficult to convey in photographs, such as nature s power or the miracle of growth. The thesis suggests, that in the third case the concept of nature broke away from its strict interconnection with the natural environment and led to a contemplation of nature that is perceivable in a person. In this context the photograph and the photographization are interpreted as an attempt to understand a person and his or her very existence in the world, while this same existential wonder is seen as being embodied in Inha s portrait of a rune singer and in his photographs of forest interior and water. Further, the thesis asks whether photographing nature could be interpreted as an action similar to the idea of the phenomenological reduction as a means of bypassing the photographer s prevailing way of being.

Filter Optimization for Grid Interactive Voltage Source Inverters

Higher order LCL filters are essential in meeting the interconnection standard requirement for grid-connected voltage source converters. LCL filters offer better harmonic attenuation and better efficiency at a smaller size when compared to the traditional L filters. The focus of this paper is to analyze the LCL filter design procedure from the point of view of power loss and efficiency. The IEEE 1547-2008 specifications for high-frequency current ripple are used as a major constraint early in the design to ensure that all subsequent optimizations are still compliant with the standards. Power loss in each individual filter component is calculated on a per-phase basis. The total inductance per unit of the LCL filter is varied, and LCL parameter values which give the highest efficiency while simultaneously meeting the stringent standard requirements are identified. The power loss and harmonic output spectrum of the grid-connected LCL filter is experimentally verified, and measurements confirm the predicted trends.

A Resonant Integrator Based PLL and AC Current Controller for Single Phase Grid Connected PWM-VSI

Grid connected PWM-VSIs are being increasingly used for applications such as Distributed Generation (DG), power quality, UPS etc. Appropriate control strategies for grid synchronisation and line current regulation are required to establish such a grid interconnection and power transfer. Control of three phase VSIs is widely reported in iterature. Conventionally, dq control in Synchronous Reference Frame(SRF) is employed for both PLL and line current control where PI-controllers are used to track the DC references. Single phase systems do not have defined direct (d) and quadrature (q) axis components that are required for SRF transformation. Thus, references are AC in nature and hence usage of PI controllers cannot yield zero steady state errors. Resonant controllers have the ability to track AC references accurately. In this work, a resonant controller based single phase PLL and current control technique are being employed for tracking grid frequency and the AC current reference respectively. A single phase full bridge converter is being operated as a STATCOM for performance evaluation of the control scheme.

Load balancing algorithms for an extended hypercube

Reduction of the execution time of a job through equitable distribution of work load among the processors in a distributed system is the goal of load balancing. Performance of static and dynamic load balancing algorithms for the extended hypercube, is discussed. Threshold algorithms are very well-known algorithms for dynamic load balancing in distributed systems. An extension of the threshold algorithm, called the multilevel threshold algorithm, has been proposed. The hierarchical interconnection network of the extended hypercube is suitable for implementing the proposed algorithm. The new algorithm has been implemented on a transputer-based system and the performance of the algorithm for an extended hypercube is compared with those for mesh and binary hypercube networks

18-Bit binary inductive voltage divider for self balancing ac bridge applications

The constructional details of an 18-bit binary inductive voltage divider (IVD) for a.c. bridge applications is described. Simplified construction with less number of windings, interconnection of winding through SPDT solid state relays instead of DPDT relays, improves reliability of IVD. High accuracy for most precision measurement achieved without D/A converters. The checks for self consistency in voltage division shows that the error is less than 2 counts in 2(18).

A Cache coherence protocol for MIN-based multiprocessors

In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches: private-blocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.

Queuing strategies for qos management of traffic between lans interconnected by low-speed wan links

We provide a comparative performance evaluation of packet queuing and link admission strategies for low-speed wide area network Links (e.g. 9600 bps, 64 kbps) that interconnect relatively highspeed, connectionless local area networks (e.g. 10 Mbps). In particular, we are concerned with the problem of providing differential quality of service to interLAN remote terminal and file transfer sessions, and throughput fairness between interLAN file transfer sessions. We use analytical and simulation models to study a variety of strategies. Our work also serves to address the performance comparison of connectionless vs. connection-oriented interconnection of CLNS LANS. When provision of priority at the physical transmission level is not feasible, we show, for low-speed WAN links (e.g. 9600 bps), the superiority of connection-oriented interconnection of connectionless LANs, with segregation of traffic streams with different QoS requirements into different window flow controlled connections. Such an implementation can easily be obtained by transporting IP packets over an X.25 WAN. For 64 kbps WAN links, there is a drop in file transfer throughputs, owing to connection overheads, but the other advantages are retained, The same solution also helps to provide throughput fairness between interLAN file transfer sessions. We also provide a corroboration of some of our modelling results with results from an experimental test-bed.

Synthesis of ASIPs for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. (C) 1999 Elsevier Science B.V. All rights reserved.

Distributed Simulation Of Flexible Manufacturing Systems

Flexible Manufacturing Systems (FMS), widely considered as the manufacturing technology of the future, are gaining increasing importance due to the immense advantages they provide in terms of cost, quality and productivity over the conventional manufacturing. An FMS is a complex interconnection of capital intensive resources and high levels of system performance is very crucial for survival in a competing environment.Discrete event simulation is one of the most popular methods for performance evaluation of FMS during planning, design and operation phases. Indeed fast simulators are suggested for selection of optimal strategies for flow control (which part type to enter and at what instant), AGV scheduling (which vehicle to carry which part), routing (which machine to process the part) and part selection (which part for processing next). In this paper we develop a C-net based model for an FMS and use the same for distributed discrete event simulation. We illustrate using examples the efficacy of destributed discrete event simulation for the performance evaluation of FMSs.

Synthesis of configurable architectures for DSP algorithms

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.

USHA: unified software and hardware architecture for video decoding

Video decoders used in emerging applications need to be flexible to handle a large variety of video formats and deliver scalable performance to handle wide variations in workloads. In this paper we propose a unified software and hardware architecture for video decoding to achieve scalable performance with flexibility. The light weight processor tiles and the reconfigurable hardware tiles in our architecture enable software and hardware implementations to co-exist, while a programmable interconnect enables dynamic interconnection of the tiles. Our process network oriented compilation flow achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi-processor, semi hardware and full hardware implementations of a video decoder. An application quality of service aware scheduler monitors and controls the operation of the entire system. We prove the concept through a prototype of the architecture on an off-the-shelf FPGA. The FPGA prototype shows a scaling in performance from QCIF to 1080p resolutions in four discrete steps. We also demonstrate that the reconfiguration time is short enough to allow migration from one configuration to the other without any frame loss.

Integrated higher-order pulse-width modulation filter-transformer structure for single-phase static compensator

A power filter is necessary to connect the output of a power converter to the grid so as to reduce the harmonic distortion introduced in the line current and voltage by the power converter. Many a times, a transformer is also present before the point of common coupling. Magnetic components often constitute a significant part of the overall weight, size and cost of the grid interface scheme. So, a compact inexpensive design is desirable. A higher-order LCL-filter and a transformer are increasingly being considered for grid interconnection of the power converter. This study proposes a design method based on a three-winding transformer, that generates an integrated structure that behaves as an LCL-filter, with both the filter inductances and the transformer that are merged into a single electromagnetic component. The parameters of the transformer are derived analytically. It is shown that along with a filter capacitor, the transformer parameters provide the filtering action of an LCL-filter. A single-phase full-bridge power converter is operated as a static compensator for performance evaluation of the integrated filter transformer. A resonant integrator-based single-phase phase locked loop and stationary frame AC current controller are employed for grid frequency synchronisation and line current control, respectively.

Thermal Strain Analysis of a Flip-Chip Package by a Modified Hybrid Method

介绍一种可用于微电子封装局部应变场分析的实验/计算混合方法,该方法结合了有限元的整体/局部模型和实时的激光云纹干涉技术,利用激光云纹干涉技术所测得的应变场来校核有限元整体模型的计算结果,并用整体模型的结果作为局部模型的边界条件,对实验难以确定的封装结构局部位置的应力、应变场进行分析.用这种方法对可控坍塌倒装封装结构在热载荷作用下焊球内的应变场分布进行了分析,结果表明该方法能够提供封装结构内应力-应变场分布的准确和可靠的结果,为微电子封装的可靠性分析提供重要的依据. For the reliability analysis of electronic packages, strains in very localized areas, such as an interconnection or a corner, need to be determined. In this paper, a modified hybrid method of global/local modeling and real time moire interferometry is presented. In this method, a simplified, coarsely meshed global model is developed to get rough information about the deformation of the microelectronic package. In order to make sure the global model has been reasonably simplified and the material properties ...