The Design and Implementation of Loudspeaker Control Network Protocols

The networking and digitalization of audio equipment has created a need for control protocols. These protocols offer new services to customers and ensure that the equipment operates correctly. The control protocols used in the computer networks are not directly applicable since embedded systems have resource and cost limitations. In this master's thesis the design and implementation of new loudspeaker control network protocols are presented. The protocol stack was required to be reliable, have short response times, configure the network automatically and support the dynamic addition and removal of loudspeakers. The implemented protocol stack was also required to be as efficient and lightweight as possible because the network nodes are fairly simple and lack processing power. The protocol stack was thoroughly tested, validated and verified. The protocols were formally described using LOTOS (Language of Temporal Ordering Specifications) and verified using reachability analysis. A prototype of the loudspeaker network was built and used for testing the operation and the performance of the control protocols. The implemented control protocol stack met the design specifications and proved to be highly reliable and efficient.

A Co-Processor Approach for Efficient Java Execution in Embedded Systems

This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource constrained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simultaneously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point support can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesigning the communication modules. Besides the virtual machine and the related co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA environment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational performance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests.

RTOS Framework for Real-Time Control System

This thesis is done as a complementary part for the active magnet bearing (AMB) control software development project in Lappeenranta University of Technology. The main focus of the thesis is to examine an idea of a real-time operating system (RTOS) framework that operates in a dedicated digital signal processor (DSP) environment. General use real-time operating systems do not necessarily provide sufficient platform for periodic control algorithm utilisation. In addition, application program interfaces found in real-time operating systems are commonly non-existent or provided as chip-support libraries, thus hindering platform independent software development. Hence, two divergent real-time operating systems and additional periodic extension software with the framework design are examined to find solutions for the research problems. The research is discharged by; tracing the selected real-time operating system, formulating requirements for the system, and designing the real-time operating system framework (OSFW). The OSFW is formed by programming the framework and conjoining the outcome with the RTOS and the periodic extension. The system is tested and functionality of the software is evaluated in theoretical context of the Rate Monotonic Scheduling (RMS) theory. The performance of the OSFW and substance of the approach are discussed in contrast to the research theme. The findings of the thesis demonstrates that the forged real-time operating system framework is a viable groundwork solution for periodic control applications.

Control d'il·luminació i ventilació d'un pàrquing

El treball presentat ve motivat per la necessitat d’instal•lació d’un pàrquing públic i privat de nova construcció a nivell d’il•luminació i ventilació. Per poder satisfer les necessitats del nostre client d’estalvi energètic i confort en l’edifici es decideix d’implementar una instal•lació immòtica que és l’aplicació de tècniques de gestió i control automatitzat a un edifici terciari amb bus de comunicació KNX/EIB. Per a la il•luminació s’han utilitzat fluorescents amb balasts DALI, que permeten la seva regulació i control, per així poder adequar en tot moment l’encesa i intensitat de llum d’aquests. En quant a la ventilació s’han utilitzat variadors de freqüència per també poder optimitzar el funcionament dels ventiladors podent posar-los en marxa quan realment sigui necessari i a la potència que calgui. Per enllaçar tots els elements de la instal•lació, detectors i actuadors, sorgeig la necessitat d’implementar xarxes de comunicació com el KNX/EIB, DALI, Modbus i Ethernet. Per gestionar variables, comunicacions i controlar elements, s´hi han implementen dos autòmats programables a més d’un PC integrat per la visualització i el control del pàrquing. S’ha aconseguit de realitzar un pàrquing totalment automàtic on no és necessaria l’actuació dels operaris i amb les principals càrregues elèctriques totalment regulables en potència. S’ha comprovat que la instal•lació funciona per sota de la potència nominal de les càrregues amb l’estalvi energètic que això suposa.

Customized agile development process for embedded software development

Agile software development has grown in popularity starting from the agile manifesto declared in 2001. However there is a strong belief that the agile methods are not suitable for embedded, critical or real-time software development, even though multiple studies and cases show differently. This thesis will present a custom agile process that can be used in embedded software development. The reasons for presumed unfitness of agile methods in embedded software development have mainly based on the feeling of these methods providing no real control, no strict discipline and less rigor engineering practices. One starting point is to provide a light process with disciplined approach to the embedded software development. Agile software development has gained popularity due to the fact that there are still big issues in software development as a whole. Projects fail due to schedule slips, budget surpassing or failing to meet the business needs. This does not change when talking about embedded software development. These issues are still valid, with multiple new ones rising from the quite complex and hard domain the embedded software developers work in. These issues are another starting point for this thesis. The thesis is based heavily on Feature Driven Development, a software development methodology that can be seen as a runner up to the most popular agile methodologies. The FDD as such is quite process oriented and is lacking few practices considered commonly as extremely important in agile development methodologies. In order for FDD to gain acceptance in the software development community it needs to be modified and enhanced. This thesis presents an improved custom agile process that can be used in embedded software development projects with size varying from 10 to 500 persons. This process is based on Feature Driven Development and by suitable parts to Extreme Programming, Scrum and Agile Modeling. Finally this thesis will present how the new process responds to the common issues in the embedded software development. The process of creating the new process is evaluated at the retrospective and guidelines for such process creation work are introduced. These emphasize the agility also in the process development through early and frequent deliveries and the team work needed to create suitable process.

Design and Control of Permanent Magnet Synchronous Machine for Hybrid Electric Vehicle

This master’s thesis mainly focuses on the design requirements of an Electric drive for Hybrid car application and its control strategy to achieve a wide speed range. It also emphasises how the control and performance requirements are transformed into its design variables. A parallel hybrid topology is considered where an IC engine and an electric drive share a common crank shaft. A permanent magnet synchronous machine (PMSM) is used as an electric drive machine. Performance requirements are converted into Machine design variables using the vector model of PMSM. Main dimensions of the machine are arrived using analytical approach and Finite Element Analysis (FEA) is used to verify the design and performance. Vector control algorithm was used to control the machine. The control algorithm was tested in a low power PMSM using an embedded controller. A prototype of 10 kW PMSM was built according to the design values. The prototype was tested in the laboratory using a high power converter. Tests were carried out to verify different operating modes. The results were in agreement with the calculations.

Press forming of paperboard – advancement of converting tools and process control

Press forming is nowadays one of the most common industrial methods in use for producing deeper trays from paperboard. Demands for material properties like recyclability and sustainability have increased also in the packaging industry, but there are still limitations related to the formability of paperboard. A majority of recent studies have focused on material development, but the potential of the package manufacturing process can also be improved by the development of tooling and process control. In this study, advanced converting tools (die cutting tools and the press forming mould) are created for production scale paperboard tray manufacturing. Also monitoring methods that enable the production of paperboard trays with enhanced quality, and can be utilized in process control are developed. The principles for tray blank preparation, including creasing pattern and die cutting tool design are introduced. The mould heating arrangement and determination of mould clearance are investigated to improve the quality of the press formed trays. The effect of the spring back of the tray walls on the tray dimensions can be managed by adjusting the heat-related process parameters and estimating it at the mould design stage. This enables production speed optimization as the process parameters can be adjusted more freely. Real-time monitoring of pressing force by using multiple force sensors embedded in the mould structure can be utilized in the evaluation of material characteristics on a modified production machinery. Comprehensive process control can be achieved with a combination of measurement of the outer dimensions of the trays and pressing force monitoring. The control method enables detection of defects and tracking changes in the material properties. The optimized converting tools provide a basis for effective operation of the control system.

Cortical and autonomic modulation of attentional control /

Whereas the role of the anterior cingulate cortex (ACC) in cognitive control has received considerable attention, much less work has been done on the role of the ACC in autonomic regulation. Its connections through the vagus nerve to the sinoatrial node of the heart are thought to exert modulatory control over cardiovascular arousal. Therefore, ACC is not only responsible for the implementation of cognitive control, but also for the dynamic regulation of cardiovascular activity that characterizes healthy heart rate and adaptive behaviour. However, cognitive control and autonomic regulation are rarely examined together. Moreover, those studies that have examined the role of phasic vagal cardiac control in conjunction with cognitive performance have produced mixed results, finding relations for specific age groups and types of tasks but not consistently. So, while autonomic regulatory control appears to support effective cognitive performance under some conditions, it is not presently clear just what factors contribute to these relations. The goal of the present study was, therefore, to examine the relations between autonomic arousal, neural responsivity, and cognitive performance in the context of a task that required ACC support. Participants completed a primary inhibitory control task with a working memory load embedded. Pre-test cardiovascular measures were obtained, and ontask ERPs associated with response control (N2/P3) and error-related processes (ERN/Pe) were analyzed. Results indicated that response inhibition was unrelated to phasic vagal cardiac control, as indexed by respiratory sinus arrhythmia (RSA). However, higher resting RSA was associated with larger ERN ampUtude for the highest working memory load condition. This finding suggests that those individuals with greater autonomic regulatory control exhibited more robust ACC error-related responses on the most challenging task condition. On the other hand, exploratory analyses with rate pressure product (RPP), a measure of sympathetic arousal, indicated that higher pre-test RPP (i.e., more sympathetic influence) was associated with more errors on "catch" NoGo trials, i.e., NoGo trials that simultaneously followed other NoGo trials, and consequently, reqviired enhanced response control. Higher pre-test RPP was also associated with smaller amplitude ERNs for all three working memory loads and smaller ampUtude P3s for the low and medium working memory load conditions. Thus, higher pretest sympathetic arousal was associated with poorer performance on more demanding "catch" NoGo trials and less robust ACC-related electrocortical responses. The findings firom the present study highlight tiie interdependence of electrocortical and cardiovascular processes. While higher pre-test parasympathetic control seemed to relate to more robust ACC error-related responses, higher pre-test sympathetic arousal resulted in poorer inhibitory control performance and smaller ACC-generated electrocortical responses. Furthermore, these results provide a base from which to explore the relation between ACC and neuro/cardiac responses in older adults who may display greater variance due to the vulnerabihty of these systems to the normal aging process.

An Error-Localization, Validation and Optimization Tool for Embedded Code Augmentation: an Architecture Oriented Approach

Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.This dissertation contributes to an architecture oriented code validation, error localization and optimization technique assisting the embedded system designer in software debugging, to make it more effective at early detection of software bugs that are otherwise hard to detect, using the static analysis of machine codes. The focus of this work is to develop methods that automatically localize faults as well as optimize the code and thus improve the debugging process as well as quality of the code.Validation is done with the help of rules of inferences formulated for the target processor. The rules govern the occurrence of illegitimate/out of place instructions and code sequences for executing the computational and integrated peripheral functions. The stipulated rules are encoded in propositional logic formulae and their compliance is tested individually in all possible execution paths of the application programs. An incorrect sequence of machine code pattern is identified using slicing techniques on the control flow graph generated from the machine code.An algorithm to assist the compiler to eliminate the redundant bank switching codes and decide on optimum data allocation to banked memory resulting in minimum number of bank switching codes in embedded system software is proposed. A relation matrix and a state transition diagram formed for the active memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Instances of code redundancy based on the stipulated rules for the target processor are identified.This validation and optimization tool can be integrated to the system development environment. It is a novel approach independent of compiler/assembler, applicable to a wide range of processors once appropriate rules are formulated. Program states are identified mainly with machine code pattern, which drastically reduces the state space creation contributing to an improved state-of-the-art model checking. Though the technique described is general, the implementation is architecture oriented, and hence the feasibility study is conducted on PIC16F87X microcontrollers. The proposed tool will be very useful in steering novices towards correct use of difficult microcontroller features in developing embedded systems.

A Generic Software Architecture for a Domain Specific Distributed Embedded System

In this paper, we have evolved a generic software architecture for a domain specific distributed embedded system. The system under consideration belongs to the Command, Control and Communication systems domain. The systems in such domain have very long operational lifetime. The quality attributes of these systems are equally important as the functional requirements. The main guiding principle followed in this paper for evolving the software architecture has been functional independence of the modules. The quality attributes considered most important for the system are maintainability and modifiability. Architectural styles best suited for the functionally independent modules are proposed with focus on these quality attributes. The software architecture for the system is envisioned as a collection of architecture styles of the functionally independent modules identified

A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example

Architecture and other Architectures: Mapping the Production of Insular Space in the Pearl River Delta (China) and Jakarta (Indonesia)

Globalization is widely regarded as the rise of the borderless world. However in practice, true globalization points rather to a “spatial logic” by which globalization is manifested locally in the shape of insular space. Globalization in this sense is not merely about the creation of physical fragmentation of space but also the creation of social disintegration. This study tries to proof that global processes also create various forms of insular space leading also to specific social implications. In order to examine the problem this study looks at two cases: China’s Pearl River Delta (PRD) and Jakarta in Indonesia. The PRD case reveals three forms of insular space namely the modular, concealed and the hierarchical. The modular points to the form of enclosed factories where workers are vulnerable for human-right violations due to the absent of public control. The concealed refers to the production of insular space by subtle discrimination against certain social groups in urban space. And the hierarchical points to a production of insular space that is formed by an imbalanced population flow. The Jakarta case attempts to show more types of insularity in relation to the complexity of a mega-city which is shaped by a culture of exclusion. Those are dormant and hollow insularity. The dormant refers to the genesis of insular– radical – community from a culture of resistance. The last type, the hollow, points to the process of making a “pseudo community” where sense of community is not really developed as well as weak social relationship with its surrounding. Although global process creates various expressions of territorial insularization, however, this study finds that the “line of flight” is always present, where the border of insularity is crossed. The PRD’s produces vernacular modernization done by peasants which is less likely to be controlled by the politics of insularization. In Jakarta, the culture of insularization causes urban informalities that have no space, neither spatially nor socially; hence their state of ephemerality continues as a tactic of place-making. This study argues that these crossings possess the potential for reconciling venue to defuse the power of insularity.

New Architectural Models for Visibly Controllable Computing: The Relevance of Dynamic Object Oriented Architectures and Plan Based Computing Models

Traditionally, we've focussed on the question of how to make a system easy to code the first time, or perhaps on how to ease the system's continued evolution. But if we look at life cycle costs, then we must conclude that the important question is how to make a system easy to operate. To do this we need to make it easy for the operators to see what's going on and to then manipulate the system so that it does what it is supposed to. This is a radically different criterion for success. What makes a computer system visible and controllable? This is a difficult question, but it's clear that today's modern operating systems with nearly 50 million source lines of code are neither. Strikingly, the MIT Lisp Machine and its commercial successors provided almost the same functionality as today's mainstream sytsems, but with only 1 Million lines of code. This paper is a retrospective examination of the features of the Lisp Machine hardware and software system. Our key claim is that by building the Object Abstraction into the lowest tiers of the system, great synergy and clarity were obtained. It is our hope that this is a lesson that can impact tomorrow's designs. We also speculate on how the spirit of the Lisp Machine could be extended to include a comprehensive access control model and how new layers of abstraction could further enrich this model.

HLA-A Typing in formalin-fixed paraffin embedded tissue samples : towards potential retrospective analysis

El Antígeno Leucocitario Humano (HLA en inglés) ha sido descrito en muchos casos como factor de pronóstico para cáncer. La característica principal de los genes de HLA, localizados en el cromosoma 6 (6p21.3), son sus numerosos polimorfismos. Los análisis de secuencia de nucleótidos muestran que la variación está restringida predominantemente a los exones que codifican los dominios de unión a péptidos de la proteína. Por lo tanto, el polimorfismo del HLA define el repertorio de péptidos que se unen a los alotipos de HLA y este hecho define la habilidad de un individuo para responder a la exposición a muchos agentes infecciosos durante su vida. La tipificación de HLA se ha convertido en un análisis importante en clínica. Muestras de tejido embebidas en parafina y fijadas con formalina (FFPE en inglés) son recolectadas rutinariamente en oncología. Este procedimiento podría ser utilizado como una buena fuente de ADN, dado que en estudios en el pasado los ensayos de recolección de ADN no eran normalmente llevados a cabo de casi ningún tejido o muestra en procedimientos clínicos regulares. Teniendo en cuenta que el problema más importante con el ADN de muestras FFPE es la fragmentación, nosotros propusimos un nuevo método para la tipificación del alelo HLA-A desde muestras FFPE basado en las secuencias del exón 2, 3 y 4. Nosotros diseñamos un juego de 12 cebadores: cuatro para el exón 2 de HLA-A, tres para el exón 3 de HLA-A y cinco para el exón 4 de HLA-A, cada uno de acuerdo las secuencias flanqueantes de su respectivo exón y la variación en la secuencia entre diferentes alelos. 17 muestran FFPE colectadas en el Hospital Universitario de Karolinska en Estocolmo Suecia fueron sometidas a PCR y los productos fueron secuenciados. Finalmente todas las secuencias obtenidas fueron analizadas y comparadas con la base de datos del IMGT-HLA. Las muestras FFPE habían sido previamente tipificadas para HLA y los resultados fueron comparados con los de este método. De acuerdo con nuestros resultados, las muestras pudieron ser correctamente secuenciadas. Con este procedimiento, podemos concluir que nuestro estudio es el primer método de tipificación basado en secuencia que permite analizar muestras viejas de ADN de las cuales no se tiene otra fuente. Este estudio abre la posibilidad de desarrollar análisis para establecer nuevas relaciones entre HLA y diferentes enfermedades como el cáncer también.

Real-Time software control of neural stimulation in a closed loop Animat system

A recent area for investigation into the development of adaptable robot control is the use of living neuronal networks to control a mobile robot. The so-called Animat paradigm comprises a neuronal network (the ‘brain’) connected to an external embodiment (in this case a mobile robot), facilitating potentially robust, adaptable robot control and increased understanding of neural processes. Sensory input from the robot is provided to the neuronal network via stimulation on a number of electrodes embedded in a specialist Petri dish (Multi Electrode Array (MEA)); accurate control of this stimulation is vital. We present software tools allowing precise, near real-time control of electrical stimulation on MEAs, with fast switching between electrodes and the application of custom stimulus waveforms. These Linux-based tools are compatible with the widely used MEABench data acquisition system. Benefits include rapid stimulus modulation in response to neuronal activity (closed loop) and batch processing of stimulation protocols.