954 resultados para Drive-thru


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Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

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Power converters burn-in test consumes large amount of energy, which increases the cost of testing, and certification, in medium and high power application. A simple test configuration to test a PWM rectifier induction motor drive, using a Doubly Fed Induction Machine (DFIM) to circulate power back to the grid for burn-in test is presented. The test configuration makes use of only one power electronic converter, which is the converter to be tested. The test method ensures soft synchronization of DFIM and Squirrel Cage Induction Machine (SCIM). A simple volt per hertz control of the drive is sufficient for conducting the test. To synchronize the DFIM with SCIM, the rotor terminal voltage of DFIM is measured and used as an indication of speed mismatch between DFIM and SCIM. The synchronization is done when the DFIM rotor voltage is at its minimum. Analysis of the DFIM characteristics confirms that such a test can be effectively performed with smooth start up and loading of the test setup. After synchronization is obtained, the speed command to SCIM is changed in order to load the setup in motoring or regenerative mode of operation. The experimental results are presented that validates the proposed test method.

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A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five-or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H-bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

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In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n +/- 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM.

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This paper reports instability and oscillations in the stator current under light-load conditions in a practical 100-kW induction motor drive. Dead-time is shown to be a cause for such oscillations. This paper shows experimentally that these oscillations could be mitigated significantly with the help of a simple dead-time compensation scheme.

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Overmodulation introduces low-order harmonics in the output voltage of a voltage source inverter. This paper presents the effects of low-order harmonics in the stator voltage on the rotor currents of an induction motor. Rotor current waveforms are presented for various operating zones in overmodulation, including six-step mode. Harmonic spectra of stator and rotor currents are compared in six-step mode of operation. Pulsating torque is evaluated at various depths of modulation during overmodulation.

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Voltage source inverter (VSI) fed six-phase induction motor drives have high 6n +/- 1; n = odd order harmonic currents, due to absence of back emf for these currents. To suppress these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six-phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6n +/- 1; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller.

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A nearly constant switching frequency current hysteresis controller for a 2-level inverter fed induction motor drive is proposed in this paper: The salient features of this controller are fast dynamics for the current, inherent protection against overloads and less switching frequency variation. The large variation of switching frequency as in the conventional hysteresis controller is avoided by defining a current-error boundary which is obtained from the current-error trajectory of the standard space vector PWM. The current-error boundary is computed at every sampling interval based on the induction machine parameters and from the estimated fundamental stator voltage. The stator currents are always monitored and when the current-error exceeds the boundary, voltage space vector is switched to reduce the current-error. The proposed boundary computation algorithm is applicable in linear and over-modulation region and it is simple to implement in any standard digital signal processor: Detailed experimental verification is done using a 7.5 kW induction motor and the results are given to show the performance of the drive at various operating conditions and validate the proposed advantages.

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A space vector-based hysteresis current controller for any general n-level three phase inverter fed induction motor drive is proposed in this study. It offers fast dynamics, inherent overload protection and low harmonic distortion for the phase voltages and currents. The controller performs online current error boundary calculations and a nearly constant switching frequency is obtained throughout the linear modulation range. The proposed scheme uses only the adjacent voltage vectors of the present sector, similar to space vector pulse-width modulation and exhibits fast dynamic behaviour under different transient conditions. The steps involved in the boundary calculation include the estimation of phase voltages from the current ripple, computation of switching time and voltage error vectors. Experimental results are given to show the performance of the drive at various speeds, effect of sudden change of the load, acceleration, speed reversal and validate the proposed advantages.

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In this paper, a current error space vector (CESV) based hysteresis controller for a 12-sided polygonal voltage space vector inverter fed induction motor (IM) drive is proposed, for the first time. An open-end winding configuration is used for the induction motor. The proposed controller uses parabolic boundary with generalized vector selection logic for all sectors. The drive scheme is first studied with a space vector based PWM (SVPWM) control and from this the current error space phasor boundary is obtained. This current error space phasor boundary is approximated with four parabolas and then the system is run with space phasor based hysteresis PWM controller by limiting the CESV within the parabolic boundary. The proposed controller has increased modulation range, absence of 5th and 7th order harmonics for the entire modulation range, nearly constant switching frequency, fast dynamic response with smooth transition to the over modulation region and a simple controller implementation.

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Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n +/- 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n +/- 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

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This paper reports instability and oscillations in the stator current under light-load conditions in a practical 100-kW induction motor drive. Dead-time is shown to be a cause for such oscillations. This paper shows experimentally that these oscillations could be mitigated significantly with the help of a simple dead-time compensation scheme.

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This paper demonstrates light-load instability in open-loop induction motor drives on account of inverter dead-time. The dynamic equations of an inverter fed induction motor, incorporating the effect of dead-time, are considered. A procedure to derive the small-signal model of the motor, including the effect of inverter dead-time, is presented. Further, stability analysis is carried out on a 100-kW, 415V, 3-phase induction motor considering no-load. For voltage to frequency (i.e. V/f) ratios between 0.5 and 1 pu, the analysis brings out regions of instability on the V-f plane, in the frequency range between 5Hz and 20Hz. Simulation and experimental results show sub-harmonic oscillations in the motor current in this region, confirming instability as predicted by the analysis.

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Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

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In this paper, a 5th and 7th harmonic suppression technique for a 2-level VSI fed IM drive, by using capacitive filtering is proposed. A capacitor fed 2-level inverter is used on an open-end winding induction motor to suppress all 5th and 7th order harmonics. A PWM scheme that maintains the capacitor voltage, while suppressing the harmonics is also proposed. The proposed scheme is valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter.