High-current inductors for high-power automotive DC-DC converters

This thesis is focused on the investigation of magnetic materials for high-power dcdc converters in hybrid and fuel cell vehicles and the development of an optimized high-power inductor for a multi-phase converter. The thesis introduces the power system architectures for hybrid and fuel cell vehicles. The requirements for power electronic converters are established and the dc-dc converter topologies of interest are introduced. A compact and efficient inductor is critical to reduce the overall cost, weight and volume of the dc-dc converter and optimize vehicle driving range and traction power. Firstly, materials suitable for a gapped CC-core inductor are analyzed and investigated. A novel inductor-design algorithm is developed and automated in order to compare and contrast the various magnetic materials over a range of frequencies and ripple ratios. The algorithm is developed for foil-wound inductors with gapped CC-cores in the low (10 kHz) to medium (30 kHz) frequency range and investigates the materials in a natural-convection-cooled environment. The practical effects of frequency, ripple, air-gap fringing, and thermal configuration are investigated next for the iron-based amorphous metal and 6.5 % silicon steel materials. A 2.5 kW converter is built to verify the optimum material selection and thermal configuration over the frequency range and ripple ratios of interest. Inductor size can increase in both of these laminated materials due to increased airgap fringing losses. Distributing the airgap is demonstrated to reduce the inductor losses and size but has practical limitations for iron-based amorphous metal cores. The effects of the manufacturing process are shown to degrade the iron-based amorphous metal multi-cut core loss. The experimental results also suggest that gap loss is not a significant consideration in these experiments. The predicted losses by the equation developed by Reuben Lee and cited by Colonel McLyman are significantly higher than the experimental results suggest. Iron-based amorphous metal has better preformance than 6.5 % silicon steel when a single cut core and natural-convection-cooling are used. Conduction cooling, rather than natural convection, can result in the highest power density inductor. The cooling for these laminated materials is very dependent on the direction of the lamination and the component mounting. Experimental results are produced showing the effects of lamination direction on the cooling path. A significant temperature reduction is demonstrated for conduction cooling versus natural-convection cooling. Iron-based amorphous metal and 6.5% silicon steel are competitive materials when conduction cooled. A novel inductor design algorithm is developed for foil-wound inductors with gapped CC-cores for conduction cooling of core and copper. Again, conduction cooling, rather than natural convection, is shown to reduce the size and weight of the inductor. The weight of the 6.5 % silicon steel inductor is reduced by around a factor of ten compared to natural-convection cooling due to the high thermal conductivity of the material. The conduction cooling algorithm is used to develop high-power custom inductors for use in a high power multi-phase boost converter. Finally, a high power digitally-controlled multi-phase boost converter system is designed and constructed to test the high-power inductors. The performance of the inductors is compared to the predictions used in the design process and very good correlation is achieved. The thesis results have been documented at IEEE APEC, PESC and IAS conferences in 2007 and at the IEEE EPE conference in 2008.

Muscle-specific variations in use-dependent crossed-facilitation of corticospinal pathways mediated by transcranial direct current (DC) stimulation

The tendency for contractions of muscles in the upper limb to give rise to increases in the excitability of corticospinal projections to the homologous muscles of the opposite limb is well known. Although the suppression of this tendency is integral to tasks of daily living, its exploitation may prove to be critical in the rehabilitation of acquired hemiplegias. Transcranial direct current (DC) stimulation induces changes in cortical excitability that outlast the period of application. We present evidence that changes in the reactivity of the corticospinal pathway induced by DC stimulation of the motor cortex interact systematically with those brought about by contraction of the muscles of the ipsilateral limb. During the application of flexion torques (up to 50% of maximum) applied at the left wrist, motor evoked potentials (MEPs) were evoked in the quiescent muscles of the right arm by magnetic stimulation of the left motor cortex (M1). The MEPs were obtained prior to and following 10 min of anodal, cathodal or sham DC stimulation of left M1. Cathodal stimulation counteracted increases in the crossed-facilitation of projections to the (right) wrist flexors that otherwise occurred as a result of repeated flexion contractions at the left wrist. In addition, cathodal stimulation markedly decreased the excitability of corticospinal projections to the wrist extensors of the right limb. Thus changes in corticospinal excitability induced by DC stimulation can be shaped (i.e. differentiated by muscle group) by focal contractions of muscles in the limb ipsilateral to the site of stimulation. (C) 2008 Elsevier Ireland Ltd. All rights reserved.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

Electrical properties of polymer/metal interface in polymer light-emitting devices: electron injection barrier suppression

The electrical characterization of a high efficient multilayer polymer light emitting diode using poly[(2-methoxy-5-hexyloxy)-p-phenylenevinylene] as the emissive layer and an anionic fluorinated surfactant as the electron transport layer was performed. For the sake of comparison, a conventional single layer device was fabricated. The density current vs. voltage measurements revealed that the conventional device has a higher threshold voltage and lower current compared to the surfactant modified device. The effective barrier height for electron injection was suppressed. The influence of the interfaces and bulk contributions to the dc and high frequencies conductivities of the devices was also discussed. (c) 2006 Springer Science + Business Media, Inc.

High current-density anodic electro-dissolution in flow-injection systems for the determination of aluminium, copper and zinc in non-ferroalloys by flame atomic absorption spectrometry

An automatic Procedure with a high current-density anodic electrodissolution unit (HDAE) is proposed for the determination of aluminium, copper and zinc in non-ferroalloys by flame atonic absorption spectrometry, based on the direct solid analysis. It consists of solenoid valve-based commutation in a flow-injection system for on-line sample electro-dissolution and calibration with one multi-element standard, an electrolytic cell equipped with two electrodes (a silver needle acts as cathode, and sample as anode), and an intelligent unit. The latter is assembled in a PC-compatible microcomputer for instrument control, and far data acquisition and processing. General management of the process is achieved by use of software written in Pascal. Electrolyte compositions, flow rates, commutation times, applied current and electrolysis time mere investigated. A 0.5 mol l(-1) HNO3 solution was elected as electrolyte and 300 A/cm(2) as the continuous current pulse. The performance of the proposed system was evaluated by analysing aluminium in Al-allay samples, and copper/zinc in brass and bronze samples, respectively. The system handles about 50 samples per hour. Results are precise (R.S.D < 2%) and in agreement with those obtained by ICP-AES and spectrophotometry at a 95% confidence level.

A DC-DC converter based on the three-state switching cell for high current and voltage step-down applications

This paper presents a pulsewidth modulation dc-dc nonisolated buck converter using the three-state switching cell, constituted by two active switches, two diodes, and two coupled inductors. Only part of the load power is processed by the active switches, reducing the peak current through the switches to half of the load current, as higher power levels can then be achieved by the proposed topology. The volume of reactive elements, i.e., inductors and capacitors, is also decreased since the ripple frequency of the output voltage is twice the switching frequency. Due to the intrinsic characteristics of the topology, total losses are distributed among all semiconductors. Another advantage of this converter is the reduced region for discontinuous conduction mode when compared to the conventional buck converter or, in other words, the operation range in continuous conduction mode is increased, as demonstrated by the static gain plot. The theoretical approach is detailed through qualitative and quantitative analyses by the application of the three-state switching cell to the buck converter operating in nonoverlapping mode $(D < 0.5)$. Besides, the mathematical analysis and development of an experimental prototype rated at 1 kW are carried out. The main experimental results are presented and adequately discussed to clearly identify its claimed advantages. © 1986-2012 IEEE.

Advanced Control for Very Fast DC-DC Converters Based on Hysteresis of the C-out Current

The bandwidth achievable by using voltage mode control or current mode control in switch-mode power supply is limited by the switching frequency. Fast transient response requires high switching frequency, although lower switching frequencies could be more suitable for higher efficiency. This paper proposes the use of hysteretic control of the output capacitor $(C_{out})$ current to improve the dynamic response of the buck converter. An external voltage loop is required to accurately regulate the output voltage. The design of the hysteretic loop and the voltage loop are presented. Besides, it is presented a non-invasive current sensor that allows measuring the current in the capacitor. This strategy has been applied for DVS (dynamic voltage scaling) on a 5 MHz buck converter. Experimental results validate the proposed control technique and show fast transient response from 1.5 V to 2.5 V in 2 $mu{rm s}$.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.

Transistor current -- voltage relationships : a consideration of high voltage dc operation of junction transistors with special reference to avalanche multiplication and related phenomena /

"August 6, 1963"

Evaluation of current underground injection of industrial waste in Illinois : final draft report /

"HWRIC RR 008." -- Cover.

Direct support, general support, and depot maintenance repair parts and special tools lists : welding machine, arc, AC/DC, 300 amp, transformer rectifier, constant current, base mounted (Eutectic Corp. model MD301 FED), FSN 3431-235-4728.

"October 1971."

Direct support and general support maintenance repair parts and special tools lists (including depot maintenance repair parts and special tools) : engine, with container, turbosupercharged, diesel, fuel injection, 90-degree "V" type, air-cooled, 12-cylinder, assembly; models AVDS-1790-2C, 2815-00-410-1203 and AVDS-1790-2D, 2815-00-410-1204 and AVDS-1790-2DR, 2815-00-124-5387.

"December 1977."

Operator, organizational, direct support and general support maintenance manual : welding machine, ARC, AC/DC, 300 AMP, transformer rectifier, constant current, base mounted (Eutectic Corp. model MD301 FED) FSN 3431-235-4728.

Includes index.

Operator's manual : welding machine, ARC, generator, diesel driven, single operator, remote control, 300 AMP, DC ARC, skid MTD, 60 AMP 20 V MIN, 375 AMP AT 40 V MAX, current 115 V 3 KW auxiliary power (Libby model ODW-300) FSN 3431-894-1573.

"August 1962."

Organizational, direct and general support, and depot maintenance repair parts and special tools list : welding machine, ARC, G.E.D. generator, 300 amp, DC, constant current, consistant potential, skid mounted, (Libby welding model LTO 300), FSN 3431-253-0558.

"March 1971."