Progetto e realizzazione di riferimenti in tensione simmetrici in tecnologia CMOS

La tesi tratta del progetto e della realizzazione di un riferimento in tensione simmetrico e stabile in temperatura, realizzato in tecnologia CMOS. Nella progettazione analogica ad alta precisione ha assunto sempre più importanza il problema della realizzazione di riferimenti in tensione stabili in temperatura. Nella maggior parte dei casi vengono presentati Bandgap, ovvero riferimenti in tensione che sfruttano l'andamento in temperatura dell'energy gap del silicio al fine di ottenere una tensione costante in un ampio range di temperatura. Tale architettura risulta utile nei sistemi ad alimentazione singola compresa fra 0 e Vdd essendo in grado di generare una singola tensione di riferimento del valore tipico di 1.2V. Nella tesi viene presentato un riferimento in tensione in grado di offrire le stesse prestazioni di un Bandgap per quanto riguarda la variazione in temperatura ma in grado di lavorare sia in sistemi ad alimentazione singola che ad alimentazione duale. Il circuito proposto e' in grado di generare due tensioni, simmetriche rispetto a un riferimento dato, del valore nominale di ±450mV. All'interno della tesi viene descritto il progetto di due diverse architetture, entrambe in grado di generare le tensioni con le specifiche richieste. Le due architetture sono poi state confrontate analizzando in particolare la stabilità in temperatura, la potenza dissipata, il PSRR (Power Supply Rejection Ratio) e la simmetria delle tensioni generate. Al termine dell'analisi è stato poi implementato su silicio il circuito che garantiva le prestazioni migliori. In sede di disegno del layout su silicio sono stati affrontati i problemi derivanti dall'adattamento dei componenti al fine di ottenere una maggiore insensibilità del circuito stesso alle incertezze legate al processo di realizzazione. Infine sono state effettuate le misurazioni attraverso una probe station a 4 sonde per verificare il corretto funzionamento del circuito e le sue prestazioni.

Advanced CMOS Interfaces for Bio-Nanosensors

The improvement of devices provided by Nanotechnology has put forward new classes of sensors, called bio-nanosensors, which are very promising for the detection of biochemical molecules in a large variety of applications. Their use in lab-on-a-chip could gives rise to new opportunities in many fields, from health-care and bio-warfare to environmental and high-throughput screening for pharmaceutical industry. Bio-nanosensors have great advantages in terms of cost, performance, and parallelization. Indeed, they require very low quantities of reagents and improve the overall signal-to-noise-ratio due to increase of binding signal variations vs. area and reduction of stray capacitances. Additionally, they give rise to new challenges, such as the need to design high-performance low-noise integrated electronic interfaces. This thesis is related to the design of high-performance advanced CMOS interfaces for electrochemical bio-nanosensors. The main focus of the thesis is: 1) critical analysis of noise in sensing interfaces, 2) devising new techniques for noise reduction in discrete-time approaches, 3) developing new architectures for low-noise, low-power sensing interfaces. The manuscript reports a multi-project activity focusing on low-noise design and presents two developed integrated circuits (ICs) as examples of advanced CMOS interfaces for bio-nanosensors. The first project concerns low-noise current-sensing interface for DC and transient measurements of electrophysiological signals. The focus of this research activity is on the noise optimization of the electronic interface. A new noise reduction technique has been developed so as to realize an integrated CMOS interfaces with performance comparable with state-of-the-art instrumentations. The second project intends to realize a stand-alone, high-accuracy electrochemical impedance spectroscopy interface. The system is tailored for conductivity-temperature-depth sensors in environmental applications, as well as for bio-nanosensors. It is based on a band-pass delta-sigma technique and combines low-noise performance with low-power requirements.

Performance evaluation and characterization of symmetric capacitors with carbon black, and asymmetric capacitors using a carbon foam supported nickel electrode

This thesis evaluates a novel asymmetric capacitor incorporating a carbon foam supported nickel hydroxide positive electrode and a carbon black negative electrode. A series of symmetric capacitors were prepared to characterize the carbon black (CB) negative electrode. The influence of the binder, PTFE, content on the cell properties was evaluated. X-ray diffraction characterization of the nickel electrode during cycling is also presented. The 3 wt% and 5 wt% PTFE/CB symmetric cells were examined using cyclic voltammetry (CV) and constant current charge/discharge measurements. As compared with symmetric cells containing more PTFE, the 3 wt% cell has the highest average specific capacitance, energy density and power density over 300 cycles, 121.8 F/g, 6.44 Wh/kg, and 604.1 W/kg, respectively. Over the 3 to 10 wt% PTFE/CB range, the 3 wt% sample exhibited the lowest effective resistance and the highest BET surface area. Three asymmetric cells (3 wt% PTFE/CB negative electrode and a nickel positive) were fabricated; cycle life was examined at 3 current densities. The highest average energy and power densities over 1000 cycles were 20 Wh/kg (21 mA/cm2) and 715 W/kg (31 mA/cm2), respectively. The longest cycle life was 11,505 cycles (at 8 mA/cm2), with an average efficiency of 79% and an average energy density of 14 Wh/kg. The XRD results demonstrate that the cathodically deposited nickel electrode is a typical α-Ni(OH)2 with the R3m structure (ABBCCA stacking); the charged electrodes are 3γ-NiOOH with the same stacking as the α-type; the discharged electrodes (including as-formed electrode) are aged to β’-Ni(OH)2 (a disordered β) with the P3m structure (ABAB stacking). A 3γ remnant was observed.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

A 45nm CMOS DESIGN OF NEUROMORPHIC SYSTEM

Neuromorphic computing has become an emerging field in wide range of applications. Its challenge lies in developing a brain-inspired architecture that can emulate human brain and can work for real time applications. In this report a flexible neural architecture is presented which consists of 128 X 128 SRAM crossbar memory and 128 spiking neurons. For Neuron, digital integrate and fire model is used. All components are designed in 45nm technology node. The core can be configured for certain Neuron parameters, Axon types and synapses states and are fully digitally implemented. Learning for this architecture is done offline. To train this circuit a well-known algorithm Restricted Boltzmann Machine (RBM) is used and linear classifiers are trained at the output of RBM. Finally, circuit was tested for handwritten digit recognition application. Future prospects for this architecture are also discussed.

The new CMOS Tracking Camera used at the Zimmerwald Observatory

During the last years the use of tracking cameras for SLR observations became less important due to the high accuracy of the predicted orbits. Upcoming new targets like satellites in eccentric orbits and space debris objects, however, require tracking cameras again. In 2013 the interline CCD camera was replaced at the Zimmerwald Observatory with a so called scientific CMOS camera. This technology promises a better performance for this application than all kinds of CCD cameras. After the comparison of the different technologies the focus will be on the integration in the Zimmerwald SLR system.

Improved Space Object Orbit Determination Using CMOS Detectors

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration,and the potential to perform image processing operations on-chip and in real-time. Here, the major challenges and design drivers for ground-based and space-based optical observation strategies for objects in Earth orbit have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and spacebased strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey assuming a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris was simulated.

Characterization of HFO2 Capacitors

Hafnium oxide (HfOn) is a promising dielectric for future microelectronic applications. Hf02 thin films (10-75nm) were deposited on Pt/Si02/Si substrates by pulsed DC magnetron reactive sputtering. Top electrodes of Pt were formed by e-beam evapo- ration through an aperture mask on the samples to create MIM (Metal-Insulator-Metal) capacitors. Various processing conditions (Arloz ratio, DC power and deposition rate) and post-deposition annealing conditions (time and temperature) were investigated. The structure of the Hf02 films was characterized by X-ray diffraction (XRD) and the roughness was measured by a profilometer. The electrical properties were characterized in terms of their relative permittivity (E,(T) and ~,.(f)) and leakage behavior (I-V, I-T and I- time). The electrical measurements were performed over a temperature range from -5 to 200°C. For the samples with best experimental results, the relative permittivity of HfOa was found to be -- 27 after anneal and increased by 0.027%/"C with increasing temperature over the measured temperature range. At 25"C, leakage current density was below lop8 ~ l c m ' at 1 volt. The leakage current increased with temperature above a specific threshold temperature below which the leakage current didn't change much. The leakage current increased with voltage. At voltages below lvolt, it's ohmic; at higher voltages, it follows Schottky model. The breakdown field is - 1 . 8 2 ~ lo6 Vlcm. The optical bandgap was measured with samples deposited on quartz substrates to be 5.4eV after anneal.

Diseño, Implementación y Verificación de un Sensor de Temperatura CMOS de Bajo Coste y Alta Funcionalidad

En este proyecto, se presenta un sensor de temperatura integrado CMOS basado en la medida de una variable secundaria, cuyo valor es dependiente de la temperatura, como es el tiempo de subida que presenta una señal eléctrica en sus flancos de subida. Con el objetivo de reducir coste y potencia consumida, el sensor integrado de temperatura propuesto genera un pulso con un ancho proporcional a la temperatura medida. Este sensor para realizar la medida elimina la necesidad de tener una señal que sirva de referencia. El área ocupada por este modelo de sensor es de 1.8967mm2, siendo éste fabricado en tecnología CMOS de 0.35µm de 4 capas de metal. Gracias a la excelente linealidad que presenta la salida digital del sensor, el error de medida alcanzado es como máximo de ±0.520ºC. La resolución efectiva mostrada en el caso peor es de 0.7ºC, y el consumo de potencia se encuentra por debajo de los 263µW, con una velocidad de realización de medidas que puede llegar a alcanzar las 1.5x10^6 medidas por segundo.

Envelope amplifier based on switching capacitors for high efficiency RF amplifiers

Modern transmitters usually have to amplify and transmit signals with simultaneous envelope and phase modulation. Due to this property of the transmitted signal, linear power amplifiers (class A, B, or AB) are usually used as a solution for the power amplifier stage. These amplifiers have high linearity, but suffer from low efficiency when the transmitted signal has high peak-to-average power ratio. The Kahn envelope elimination and restoration technique is used to enhance the efficiency of RF transmitters, by combining highly efficient, nonlinear RF amplifier (class E) with a highly efficient envelope amplifier in order to obtain a linear and highly efficient RF amplifier. This paper presents a solution for the envelope amplifier based on a multilevel converter in series with a linear regulator. The multilevel converter is implemented by employing voltage dividers based on switching capacitors. The implemented envelope amplifier can reproduce any signal with a maximum spectral component of 2 MHz and give instantaneous maximum power of 50 W. The efficiency measurements show that when the signals with low average value are transmitted, the implemented prototypes have up to 20% higher efficiency than linear regulators used as a conventional solution.

A 0.0016 mm(2) 0.64 nJ leakage-based CMOS temperature sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C.

Receptores homodinos a 300 GHz basados en tecnología CMOS

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and its performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

300 GHz CMOS video detection using broadband and active planar antennas

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

A built-in CMOS Total Ionization Dose smart sensor

Total Ionization Dose (TID) is traditionally measured by radiation sensitive FETs (RADFETs) that require a radiation hardened Analog-to-Digital Converter (ADC) stage. This work introduces a TID sensor based on a delay path whose propagation time is sensitive to the absorbed radiation. It presents the following advantages: it is a digital sensor able to be integrated in CMOS circuits and programmable systems such as FPGAs; it has a configurable sensitivity that allows to use this device for radiation doses ranging from very low to relatively high levels; its interface helps to integrate this sensor in a multidisciplinary sensor network; it is self-timed, hence it does not need a clock signal that can degrade its accuracy. The sensor has been prototyped in a 0.35μm technology, has an area of 0.047mm2, of which 22% is dedicated to measuring radiation, and an energy per conversion of 463pJ. Experimental irradiation tests have validated the correct response of the proposed TID sensor.