基于STM-64的甚短距离并行光传输系统

研究了STM-64数据帧的转换映射技术,利用垂直腔面发射激光器(VCSEL)列阵光源和PIN列阵探测器成功研制出10 Gb/s的甚短距离12信道SDH并行光传输系统,该系统结构紧凑,具有检错和纠错功能。跟传统的10 Gb/s串行光传输系统相比,本系统降低了对单路器件传输性能的要求。经SDH传输测试仪测试,系统能实现无误传输。

64通道100ps时间-数字变换模块的研制

兰州重离子加速器冷却储存环外靶实验终端的多丝漂移室通过测量带电粒子的漂移时间得到径迹信息。本文介绍的64通道高精度时间-数字变换模块,采用高密度的连接器和多通道的时间-数字变换芯片HPTDC,模块的数据通过PXI总线传输到计算机,时间精度可达100ps。

平板型光电倍增管64路信号的简化处理

HAMAMATSU的H8500型64路多阳极平板型光电倍增管以其非常优越的位置分辨被广泛地应用于各种小型探测装置和大型阵列探测装置,多信号的有效、快速和最为经济的简化电子学线路读出成为多阳极光电倍增管非常重要的研究内容。基于DPC电桥简化处理多阳极光电倍增管信号,在未采用铅准直的情况下测量137Csγ源最好位置分辨(FWHM)达到了2mm左右。

Projectile fragmentation of Kr-86 at 64 MeV/nucleon

We measured fragmentation cross sections produced using the primary beam of Kr-86 at 64 MeV/nucleon on Be-9 and Ta-181 targets. The cross sections were obtained by integrating the momentum distributions of isotopes with 25 <= Z <= 36 measured using the RIPS fragment separator at RIKEN. The cross-section ratios obtained with the Ta-181 and Be-9 targets depend on the fragment masses, contrary to the simple geometrical models. We compared the extracted cross sections to EPAX; an empirical parametrization of fragmentation cross sections. Predictions from current EPAX parametrization severely overestimate the production cross sections of very neutron-rich isotopes. Attempts to obtain another set of EPAX parameters specific to the reaction studied here to extrapolate the neutron-rich nuclei more accurately have not been very successful, suggesting that accurate predictions of production cross sections of nuclei far from the valley of stability require information of nuclear properties that are not present in EPAX.

64通道一维位置灵敏电流分布探测器及其数据获取系统；A 64-Channel Position Sensitive Current Distribution Detector with Data Acquisition System

针对高流强粒子束与绝缘毛细管相互作用的特点,设计制作了一套64通道一维位置灵敏电流分布探测器及其配套的数据获取系统,该探测器可分辨最小直径为1mm的束斑,通过数据获取系统可实现可视化自动数据采集。用2nA和200—2000eV电子对探测器进行了定标,并用10μA和2000eV的电子束穿越锥形毛细管后的出射电子,对探测器及数据获取系统进行测试,获得了出射粒子的位置分布谱及能量信息。

（一）兰州重离子加速器束流能量、能散测量（二）中能~(12)C + ~(64)Ni, ~(58)Ni碎裂反应的实验研究

本论文通过讨论选择了简单易行的弹性散射法来测量兰州重离子加速器流能量、能散，描述了整个实验的准备、进行及数据处理，并讨论、修正了所得的实验结果，得到了~(12)C束流能散为(2.74 ± 0.14) * 10~(-2)，能量经刻度为每核子46.4MeV/u。本工作还拟采用飞行时间法来测量束流能量的绝对值，以检验弹性散射法测得的能量值，而且已设计制作了用作起始探测器的微道板（MCP）零时探测器，上器进行了必要的高调试，用MCP零时探测器作为起始探测器，Si半导体探测器作为终止探测器，对于10MeV/uα粒子，得到了好于560ps的总时间分辩，完全可用于中能重离子实验探测

UNUSUAL VOLTAMMETRIC BEHAVIOR OF AN ELECTROCHEMICALLY SYNTHESIZED CONDUCTING PLATINUM CLUSTER COMPOUND K-1.64[PT(C2O4)(2)]

The compound K-1.64[Pt(C2O4)(2)] was electrochemically synthesized on a glassy carbon electrode using both single-potential step and cyclic voltammetry techniques; voltammetric behaviour of the working electrode was changed dramatically with deposition of

'We are not Seeking Strength for its Own Sake': The British Labour Party, West Germany and the Cold War, 1951-64

Hughes, R. (2002). 'We are not Seeking Strength for its Own Sake': The British Labour Party, West Germany and the Cold War, 1951-64. Cold War History. 3(1) pp.67-94 RAE2008

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.