988 resultados para Éthiques de soi


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This work is aimed at optimising the static performance of a high voltage SOI LDMOSFET. Starting with a conventional LDMOSFET, 2D and 3D numerical simulation models, able to accurately match datasheet values, have been developed. Moving from the original device, several design techniques have been investigated with the target of improving the breakdown voltage and the ON-state resistance. The considered design techniques are based on the modification of the doping profile of the drift region and the Superjunction design technique. The paper shows that a single step doping within the drift region is the best design choice for the considered device and is found to give a 24% improvement in the breakdown voltage and a 17% reduction of the ON-state resistance. © 2011 IEEE.

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A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

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In this paper we present a robust SOI-CMOS ethanol sensor based on a tungsten-doped lanthanum iron oxide sensing material. The device shows response to gas, has low power consumption, good uniformity, high temperature stability and can be manufactured at low cost and with integrated circuitry. The platform is a tungsten-based CMOS micro-hotplate that has been shown to be stable for over two thousand hours at a high temperature (600°C) in a form of accelerated life test. The tungsten-doped lanthanum iron oxide was deposited on the micro-hotplate as a slurry with terpineol using a syringe, dried and annealed. Preliminary gas testing was done and the material shows response to ethanol vapour. These results are promising and we believe that this combination of a robust CMOS micro-hotplate and a good sensing material can form the basis for a commercial CMOS gas sensor. © 2011 Published by Elsevier Ltd.

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Here we report on the successful low-temperature growth of zinc oxide nanowires (ZnONWs) on silicon-on-insulator (SOI) CMOS micro-hotplates and their response, at different operating temperatures, to hydrogen in air. The SOI micro-hotplates were fabricated in a commercial CMOS foundry followed by a deep reactive ion etch (DRIE) in a MEMS foundry to form ultra-low power membranes. The micro-hotplates comprise p+ silicon micro-heaters and interdigitated metal electrodes (measuring the change in resistance of the gas sensitive nanomaterial). The ZnONWs were grown as a post-CMOS process onto the hotplates using a CMOS friendly hydrothermal method. The ZnONWs showed a good response to 500 to 5000 ppm of hydrogen in air. We believe that the integration of ZnONWs with a MEMS platform results in a low power, low cost, hydrogen sensor that would be suitable for handheld battery-operated gas sensors. © 2011 Published by Elsevier Ltd.

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This paper demonstrates and discusses novel "three dimensional" silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations. © 2012 IEEE.

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This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

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This paper introduces a pressure sensing structure configured as a stress sensitive differential amplifier (SSDA), built on a Silicon-on-Insulator (SOI) membrane. Theoretical calculation show the significant increase in sensitivity which is expected from the pressure sensors in SSDA configuration compared to the traditional Wheatstone bridge circuit. Preliminary experimental measurements, performed on individual transistors placed on the membrane, exhibit state-the-art sensitivity values (1.45mV/mbar). © 2012 IEEE.

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This paper reviews and addresses certain aspects of Silicon-On-Insulator (SOI) technologies for a harsh environment. The paper first describes the need for specialized sensors in applications such as (i) domestic and other small-scale boilers, (ii) CO2 Capture and Sequestration, (iii) oil & gas storage and transportation, and (iv) automotive. We describe in brief the advantages and special features of SOI technology for sensing applications requiring temperatures in excess of the typical bulk silicon junction temperatures of 150oC. Finally we present the concepts, structures and prototypes of simple and smart micro-hotplate and Infra Red (IR) based emitters for NDIR (Non Dispersive IR) gas sensors in harsh environments. © 2012 IEEE.

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We investigate the electrical properties of Silicon-on-Insulator photonic crystals as a function of doping level and air filling factor. A very interesting trade-off between conductivity and optical losses in L3 cavities is also found. © 2011 IEEE.

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The paper reports on the in-situ growth of zinc oxide nanowires (ZnONWs) on a complementary metal oxide semiconductor (CMOS) substrate, and their performance as a sensing element for ppm (parts per million) levels of toluene vapour in 3000 ppm humid air. Zinc oxide NWs were grown using a low temperature (only 90°C) hydrothermal method. The ZnONWs were first characterised both electrically and through scanning electron microscopy. Then the response of the on-chip ZnONWs to different concentrations of toluene (400-2600ppm) was observed in air at 300°C. Finally, their gas sensitivity was determined and found to lie between 0.1% and 0.3% per ppm. © 2013 IEEE.