Addressing the project implementation challenges in the Saudi Arabian power supply industry: an investigative approach towards improving project delivery

For many decades, the Kingdom of Saudi Arabia has been widely known for being a reliable oil exporter. This fact, however, has not exempted it from facing significant domestic energy challenges. One of the most pressing of these challenges involves bridging the widening electricity supply-demand gap where, currently, the demand is growing at a very fast rate. One crucial means to address this challenge is through delivering power supply projects with maximum efficiency. Project delivery delay, however, is not uncommon in this highly capital-intensive industry, indicating electricity supplies are not coping with the demand increases. To provide a deeper insight into the challenges of project implementation and efficient practice, this research adopts a pragmatic approach by triangulating literature, questionnaires and semi-structured interviews. The research was conducted in the Saudi Arabian power supply industry – Western Operating Area. A total of 105 usable questionnaires were collected, and 28 recorded, semi-structured interviews were conducted, analysed and synthesised to produce a conceptual model of what constitutes the project implementation challenges in the investigated industry. This was achieved by conducting a comprehensive ranking analysis applied to all 58 identified and surveyed factors which, according to project practitioners in the investigated industry, contribute to project delay. 28 of these project delay factors were selected as the "most important" ones. Factor Analysis was employed to structure these 28 most important project delay factors into the following meaningful set of 7 project implementation challenges: Saudi Electricity Company's contractual commitments, Saudi Electricity Company's communication and coordination effectiveness, contractors' project planning and project control effectiveness, consultant-related aspects, manpower challenges and material uncertainties, Saudi Electricity Company's tendering system, and lack of project requirements clarity. The study has implications for industry policy in that it provides a coherent assessment of the key project stakeholders' central problems. From this analysis, pragmatic recommendations are proposed that, if enacted, will minimise the significance of the identified problems on future project outcomes, thus helping to ensure the electricity supply-demand gap is diminished.

Wireless Power Link Design for Both High-Power Inductive Coupling and Smart Metasurfaces Exploitation

As future technologies are going to be autonomous under the umbrella of the Internet of things (IoT) we can expect WPT to be the solution for intelligent devices. WPT has many industrial and medical applications both in the near-field and far-field domains. Considering the impact of WPT, this thesis is an attempt to design and realize both near-field and far-field WPT solutions for different application scenarios. A 27 MHz high frequency inductive wireless power link has been designed together with the Class-E switching inverter to compensate for the efficiency loss because of the varying weak coupling between transmitter and receiver because of their mutual misalignment. Then a system of three coils was introduced for SWIPT. The outer coil for WPT and the inner two coils were designed to fulfil the purpose of communication and testing, operating at frequencies different from the WPT coil. In addition to that, a trapping filter technique has also been adopted to ensure the EM isolation of the coils. Moreover, a split ring resonator-based dual polarization converter has been designed with good efficiency over a wide frequency range. The gap or cuts have been introduced in the adjacent sides of the square ring to make it a dual-polarization converter. The converter is also stable over a wide range of incident angles. Furthermore, a meta-element based intelligent surface has been designed to work in the reflection mode at 5 GHz. In this research activity, interdigital capacitors (IDCs) instead of ICs are introduced and a thin layer of the HfZrO between substrate and meta elements is placed whose response can be tuned and controlled with the applied voltage to achieve IRS.

Teholähdesuunnittelu

Työssä vertaillaan massatuotannon näkökulmasta eri tehoalueille sopivia teholähteen toteuttamisvaihtoehtoja. Lisäksi esitellään standardien asettamia vaatimuksia teholähteille. Työssä käsitellään teholähdesuunnittelun eri osa-alueita ja niihin sopivien simulointityökalujen hyödyntämismahdollisuuksia suunnitteluprosessin osana. Simulointituloksia ja teoreettisia laskelmia vertaillaan prototyypistä suoritettuihin mittauksiin.

Teholähdepiirilevyn suunnittelu akkukäyttöiseen laitteeseen

Teholähdepiirilevyn suunnittelu etenkin kooltaan pieneen akkukäyttöiseen laitteeseen on monivaiheinen suunnitteluprosessi. Teholähdetopologioiden valinta levylle määrää heti alkuunsa kuinka vakaata jännitettä levyllä voidaan tuottaa, kuinka suuria tehoja siitä voidaan ottaa, miten paljon häiriöitä levy tuottaa ympäristöönsä ja ennen kaikkea, kun akkukäyttöisestä laitteesta on kysymys, kuinka hyvään hyötysuhteeseen sillä voidaan päästä. Suunnittelun kannalta hakkuriteholähde on teholähdetopologioista vaativin. Tässä työssä paneudutaankin tarkemmin boost-hakkuriteholähteen suunnitteluun. Pelkkä hakkurin komponenttien mitoitus ei takaa teholähteelle parasta mahdollista toimintaa, vaan myös piirilevysuunnittelulla on suuri merkitys. Akkukäyttöisen laitteen teholähdepiirilevyn suunnittelu ei rajoitu yksinomaan teholähteiden suunnitteluun vaan levy sisältää usein myös muuta oheiselektroniikkaa, yleensä ainakin laitteen käynnistyselektroniikan sekä akun latausjärjestelmän. Etenkin akun latausjärjestelmän suunnittelu saattaa muodostua hyvinkin monimutkaiseksi tehtäväksi. Tässä työssä onkin tutkittu muutaman yleisimmän akkutyypin latausmenetelmiä. Työssä suunnitellaan myös käytännössä teholähdepiirilevy akkukäyttöiseen mittalaitteeseen. Levyn toimintaa tutkitaan erinäisin mittauksin, joilla pyritään selvittämään levyn heikkoudet. Näiden heikkouksien pohjalta levystä suunnitellaan paranneltu versio. Tällekin levylle tehdään samat mittaukset kuin edelliselle versiolle, joista selviää parannusten onnistuminen.

FPGA-Based Control Design for Power Electronic Applications

Tehoelektoniikkalaitteella tarkoitetaan ohjaus- ja säätöjärjestelmää, jolla sähköä muokataan saatavilla olevasta muodosta haluttuun uuteen muotoon ja samalla hallitaan sähköisen tehon virtausta lähteestä käyttökohteeseen. Tämä siis eroaa signaalielektroniikasta, jossa sähköllä tyypillisesti siirretään tietoa hyödyntäen eri tiloja. Tehoelektroniikkalaitteita vertailtaessa katsotaan yleensä niiden luotettavuutta, kokoa, tehokkuutta, säätötarkkuutta ja tietysti hintaa. Tyypillisiä tehoelektroniikkalaitteita ovat taajuudenmuuttajat, UPS (Uninterruptible Power Supply) -laitteet, hitsauskoneet, induktiokuumentimet sekä erilaiset teholähteet. Perinteisesti näiden laitteiden ohjaus toteutetaan käyttäen mikroprosessoreja, ASIC- (Application Specific Integrated Circuit) tai IC (Intergrated Circuit) -piirejä sekä analogisia säätimiä. Tässä tutkimuksessa on analysoitu FPGA (Field Programmable Gate Array) -piirien soveltuvuutta tehoelektroniikan ohjaukseen. FPGA-piirien rakenne muodostuu erilaisista loogisista elementeistä ja niiden välisistä yhdysjohdoista.Loogiset elementit ovat porttipiirejä ja kiikkuja. Yhdysjohdot ja loogiset elementit ovat piirissä kiinteitä eikä koostumusta tai lukumäärää voi jälkikäteen muuttaa. Ohjelmoitavuus syntyy elementtien välisistä liitännöistä. Piirissä on lukuisia, jopa miljoonia kytkimiä, joiden asento voidaan asettaa. Siten piirin peruselementeistä voidaan muodostaa lukematon määrä erilaisia toiminnallisia kokonaisuuksia. FPGA-piirejä on pitkään käytetty kommunikointialan tuotteissa ja siksi niiden kehitys on viime vuosina ollut nopeaa. Samalla hinnat ovat pudonneet. Tästä johtuen FPGA-piiristä on tullut kiinnostava vaihtoehto myös tehoelektroniikkalaitteiden ohjaukseen. Väitöstyössä FPGA-piirien käytön soveltuvuutta on tutkittu käyttäen kahta vaativaa ja erilaista käytännön tehoelektroniikkalaitetta: taajuudenmuuttajaa ja hitsauskonetta. Molempiin testikohteisiin rakennettiin alan suomalaisten teollisuusyritysten kanssa soveltuvat prototyypit,joiden ohjauselektroniikka muutettiin FPGA-pohjaiseksi. Lisäksi kehitettiin tätä uutta tekniikkaa hyödyntävät uudentyyppiset ohjausmenetelmät. Prototyyppien toimivuutta verrattiin vastaaviin perinteisillä menetelmillä ohjattuihin kaupallisiin tuotteisiin ja havaittiin FPGA-piirien mahdollistaman rinnakkaisen laskennantuomat edut molempien tehoelektroniikkalaitteiden toimivuudessa. Työssä on myösesitetty uusia menetelmiä ja työkaluja FPGA-pohjaisen säätöjärjestelmän kehitykseen ja testaukseen. Esitetyillä menetelmillä tuotteiden kehitys saadaan mahdollisimman nopeaksi ja tehokkaaksi. Lisäksi työssä on kehitetty FPGA:n sisäinen ohjaus- ja kommunikointiväylärakenne, joka palvelee tehoelektroniikkalaitteiden ohjaussovelluksia. Uusi kommunikointirakenne edistää lisäksi jo tehtyjen osajärjestelmien uudelleen käytettävyyttä tulevissa sovelluksissa ja tuotesukupolvissa.

Analysis and design of constant-frequency peak-current-controlled high-power-factor boost rectifier with slope compensation

This paper presents the analysis and the design of a peak-current-controlled high-power-factor boost rectifier, with slope compensation, operating at constant frequency. The input current shaping is achieved, with continuous inductor current mode, with no multiplier to generate a current reference. The resulting overall circuitry is very simple, in comparison with the average-current-controlled boost rectifier. Experimental results are presented, taken from a laboratory prototype rated at 370 W and operating at 67 kHz. The measured power factor was 0.99, with a input current THD equal to 5.6%, for an input voltage THD equal to 2.26%.

Design and Optimization of Power Delivery and Distribution Systems Using Evolutionary Computation Techniques

Nowadays computing platforms consist of a very large number of components that require to be supplied with diferent voltage levels and power requirements. Even a very small platform, like a handheld computer, may contain more than twenty diferent loads and voltage regulators. The power delivery designers of these systems are required to provide, in a very short time, the right power architecture that optimizes the performance, meets electrical specifications plus cost and size targets. The appropriate selection of the architecture and converters directly defines the performance of a given solution. Therefore, the designer needs to be able to evaluate a significant number of options in order to know with good certainty whether the selected solutions meet the size, energy eficiency and cost targets. The design dificulties of selecting the right solution arise due to the wide range of power conversion products provided by diferent manufacturers. These products range from discrete components (to build converters) to complete power conversion modules that employ diferent manufacturing technologies. Consequently, in most cases it is not possible to analyze all the alternatives (combinations of power architectures and converters) that can be built. The designer has to select a limited number of converters in order to simplify the analysis. In this thesis, in order to overcome the mentioned dificulties, a new design methodology for power supply systems is proposed. This methodology integrates evolutionary computation techniques in order to make possible analyzing a large number of possibilities. This exhaustive analysis helps the designer to quickly define a set of feasible solutions and select the best trade-off in performance according to each application. The proposed approach consists of two key steps, one for the automatic generation of architectures and other for the optimized selection of components. In this thesis are detailed the implementation of these two steps. The usefulness of the methodology is corroborated by contrasting the results using real problems and experiments designed to test the limits of the algorithms.

THE DESIGN OF A POWER SYSTEM FOR A WIRELESS SENSOR NETWORK FOR LONG-TERM OPERATION

Wireless sensor networks (WSNs) have shown wide applicability to many fields including monitoring of environmental, civil, and industrial settings. WSNs however are resource constrained by many competing factors that span their hardware, software, and networking. One of the central resource constrains is the charge consumption of WSN nodes. With finite energy supplies, low charge consumption is needed to ensure long lifetimes and success of WSNs. This thesis details the design of a power system to support long-term operation of WSNs. The power system’s development occurs in parallel with a custom WSN from the Queen’s MEMS Lab (QML-WSN), with the goal of supporting a 1+ year lifetime without sacrificing functionality. The final power system design utilizes a TPS62740 DC-DC converter with AA alkaline batteries to efficiently supply the nodes while providing battery monitoring functionality and an expansion slot for future development. Testing tools for measuring current draw and charge consumption were created along with analysis and processing software. Through their use charge consumption of the power system was drastically lowered and issues in QML-WSN were identified and resolved including the proper shutdown of accelerometers, and incorrect microcontroller unit (MCU) power pin connection. Controlled current profiling revealed unexpected behaviour of nodes and detailed current-voltage relationships. These relationships were utilized with a lifetime projection model to estimate a lifetime between 521-551 days, depending on the mode of operation. The power system and QML-WSN were tested over a long term trial lasting 272+ days in an industrial testbed to monitor an air compressor pump. Environmental factors were found to influence the behaviour of nodes leading to increased charge consumption, while a node in an office setting was still operating at the conclusion of the trail. This agrees with the lifetime projection and gives a strong indication that a 1+ year lifetime is achievable. Additionally, a light-weight charge consumption model was developed which allows charge consumption information of nodes in a distributed WSN to be monitored. This model was tested in a laboratory setting demonstrating +95% accuracy for high packet reception rate WSNs across varying data rates, battery supply capacities, and runtimes up to full battery depletion.

THE DESIGN OF A POWER SYSTEM FOR A WIRELESS SENSOR NETWORK FOR LONG-TERM OPERATION

Wireless sensor networks (WSNs) have shown wide applicability to many fields including monitoring of environmental, civil, and industrial settings. WSNs however are resource constrained by many competing factors that span their hardware, software, and networking. One of the central resource constrains is the charge consumption of WSN nodes. With finite energy supplies, low charge consumption is needed to ensure long lifetimes and success of WSNs. This thesis details the design of a power system to support long-term operation of WSNs. The power system’s development occurs in parallel with a custom WSN from the Queen’s MEMS Lab (QML-WSN), with the goal of supporting a 1+ year lifetime without sacrificing functionality. The final power system design utilizes a TPS62740 DC-DC converter with AA alkaline batteries to efficiently supply the nodes while providing battery monitoring functionality and an expansion slot for future development. Testing tools for measuring current draw and charge consumption were created along with analysis and processing software. Through their use charge consumption of the power system was drastically lowered and issues in QML-WSN were identified and resolved including the proper shutdown of accelerometers, and incorrect microcontroller unit (MCU) power pin connection. Controlled current profiling revealed unexpected behaviour of nodes and detailed current-voltage relationships. These relationships were utilized with a lifetime projection model to estimate a lifetime between 521-551 days, depending on the mode of operation. The power system and QML-WSN were tested over a long term trial lasting 272+ days in an industrial testbed to monitor an air compressor pump. Environmental factors were found to influence the behaviour of nodes leading to increased charge consumption, while a node in an office setting was still operating at the conclusion of the trail. This agrees with the lifetime projection and gives a strong indication that a 1+ year lifetime is achievable. Additionally, a light-weight charge consumption model was developed which allows charge consumption information of nodes in a distributed WSN to be monitored. This model was tested in a laboratory setting demonstrating +95% accuracy for high packet reception rate WSNs across varying data rates, battery supply capacities, and runtimes up to full battery depletion.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Design and Performance Analysis of the Electrical Power System of a Petrochemical Facility

This thesis deals with the sizing and analysis of the electrical power system of a petrochemical plant. The activity was carried out in the framework of an electrical engineering internship. The sizing and electrical calculations, as well as the study of the dynamic behavior of network quantities, are accomplished by using the ETAP (Electrical Transient Analyzer Program) software. After determining the type and size of the loads, the calculation of power flows is carried out for all possible network layout and different power supply configurations. The network is normally operated in a double radial configuration. However, the sizing must be carried out taking into account the most critical configuration, i.e., the temporary one of single radial operation, and also considering the most unfavorable power supply conditions. The calculation of shortcircuit currents is then carried out and the appropriate circuit breakers are selected. Where necessary, capacitor banks are sized in order to keep power factor at the point of common coupling within the preset limits. The grounding system is sized by using the finite element method. For loads with the highest level of criticality, UPS are sized in order to ensure their operation even in the absence of the main power supply. The main faults that can occur in the plant are examined, determining the intervention times of the protections to ensure that, in case of failure on one component, the others can still properly operate. The report concludes with the dynamic and stability analysis of the power system during island operation, in order to ensure that the two gas turbines are able to support the load even during transient conditions.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Design and evaluation of multi-band RF energy harvesting circuits and antennas for WSNs

Radio frequency (RF) energy harvesting is an emerging technology that will enable to drive the next generation of wireless sensor networks (WSNs) without the need of using batteries. In this paper, we present RF energy harvesting circuits specifically developed for GSM bands (900/1800) and a wearable dual-band antenna suitable for possible implementation within clothes for body worn applications. Besides, we address the development and experimental characterization of three different prototypes of a five-stage Dickson voltage multiplier (with match impedance circuit) responsible for harvesting the RF energy. Different printed circuit board (PCB) fabrication techniques to produce the prototypes result in different values of conversion efficiency. Therefore, we conclude that if the PCB fabrication is achieved by means of a rigorous control in the photo-positive method and chemical bath procedure applied to the PCB it allows for attaining better values for the conversion efficiency. All three prototypes (1, 2 and 3) can power supply the IRIS sensor node for RF received powers of -4 dBm, -6 dBm and -5 dBm, and conversion efficiencies of 20, 32 and 26%, respectively. © 2014 IEEE.

Design of future distribution grids

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.