Phase plane theory of transistor bistable circuits /

Vita.

Transistor current -- voltage relationships : a consideration of high voltage dc operation of junction transistors with special reference to avalanche multiplication and related phenomena /

"August 6, 1963"

General Electric transistor manual.

Cover title: Transistor manual, including tunnel diodes; specifications, applications, circuits.

G E transistor manual.

Cover title: Transistor manual, including signal diodes; applications, circuits, specifications.

Iohannis Linder ... De venenis in genere & in specie exercitatio : videlicet, eorum natura & in corpus agendi modo atque eadem, pro morbi acuti vel chronici ex iisdem oborientis indole , curandi : & in esculentis, potulentisque indagandi ratione juxta veterum quorundam & recentiorum dogmata ad solidorum & fluidorum corporis organici leges mechanicas deducta & explicata.

NL,

A reverse-bias safe operating area transistor tester /

Includes bibliographical references (p. 14).

Operator, organizational, DS, GS, and depot maintenance manual : test set, transistor TS-1836B/U.

"October 1968."

Operator, organizational, field, and depot maintenance manual : transistor test set TS-1836/U.

"12 December 1983"--Change no. 3.

Operator, organizational, direct support, and general support maintenance manual : test set, transistor TS-1836C/U.

"April 1972."

Operator's, organizational, direct support and general support maintenance manual : test set, transistor TS-1836D/U, NSN 6625-00-138-7320.

"August 1975."

Transistor circuit engineering.

Mode of access: Internet.

Design and development of distributed feedback transistor lasers

The transistor laser is a unique three-port device that operates simultaneously as a transistor and a laser. With quantum wells incorporated in the base regions of heterojunction bipolar transistors, the transistor laser possesses advantageous characteristics of fast base spontaneous carrier lifetime, high differential optical gain, and electrical-optical characteristics for direct “read-out” of its optical properties. These devices have demonstrated many useful features such as high-speed optical transmission without the limitations of resonance, non-linear mixing, frequency multiplication, negative resistance, and photon-assisted switching. To date, all of these devices operate as multi-mode lasers without any type of wavelength selection or stabilizing mechanisms. Stable single-mode distributed feedback diode laser sources are important in many applications including spectroscopy, as pump sources for amplifiers and solid-state lasers, for use in coherent communication systems, and now as TLs potentially for integrated optoelectronics. The subject of this work is to expand the future applications of the transistor laser by demonstrating the theoretical background, process development and device design necessary to achieve singlelongitudinal- mode operation in a three-port transistor laser. A third-order distributed feedback surface grating is fabricated in the top emitter AlGaAs confining layers using soft photocurable nanoimprint lithography. The device produces continuous wave laser operation with a peak wavelength of 959.75 nm and threshold current of 13 mA operating at -70 °C. For devices with cleaved ends a side-mode suppression ratio greater than 25 dB has been achieved.

Measurement of finite-frequency current statistics in a single-electron transistor

Electron transport in nanoscale structures is strongly influenced by the Coulomb interaction that gives rise to correlations in the stream of charges and leaves clear fingerprints in the fluctuations of the electrical current. A complete understanding of the underlying physical processes requires measurements of the electrical fluctuations on all time and frequency scales, but experiments have so far been restricted to fixed frequency ranges, as broadband detection of current fluctuations is an inherently difficult experimental procedure. Here we demonstrate that the electrical fluctuations in a single-electron transistor can be accurately measured on all relevant frequencies using a nearby quantum point contact for on-chip real-time detection of the current pulses in the single-electron device. We have directly measured the frequency-dependent current statistics and, hereby, fully characterized the fundamental tunnelling processes in the single-electron transistor. Our experiment paves the way for future investigations of interaction and coherence-induced correlation effects in quantum transport.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.