Simulative Investigation on the Electronic, Vibrational and Optical Properties of the Ge2Sb2Te5 Chalcogenide

Chalcogenides are chemical compounds with at least one of the following three chemical elements: Sulfur (S), Selenium (Sn), and Tellurium (Te). As opposed to other materials, chalcogenide atomic arrangement can quickly and reversibly inter-change between crystalline, amorphous and liquid phases. Therefore they are also called phase change materials. As a results, chalcogenide thermal, optical, structural, electronic, electrical properties change pronouncedly and significantly with the phase they are in, leading to a host of different applications in different areas. The noticeable optical reflectivity difference between crystalline and amorphous phases has allowed optical storage devices to be made. Their very high thermal conductivity and heat fusion provided remarkable benefits in the frame of thermal energy storage for heating and cooling in residential and commercial buildings. The outstanding resistivity difference between crystalline and amorphous phases led to a significant improvement of solid state storage devices from the power consumption to the re-writability to say nothing of the shrinkability. This work focuses on a better understanding from a simulative stand point of the electronic, vibrational and optical properties for the crystalline phases (hexagonal and faced-centered cubic). The electronic properties are calculated implementing the density functional theory combined with pseudo-potentials, plane waves and the local density approximation. The phonon properties are computed using the density functional perturbation theory. The phonon dispersion and spectrum are calculated using the density functional perturbation theory. As it relates to the optical constants, the real part dielectric function is calculated through the Drude-Lorentz expression. The imaginary part results from the real part through the Kramers-Kronig transformation. The refractive index, the extinctive and absorption coefficients are analytically calculated from the dielectric function. The transmission and reflection coefficients are calculated using the Fresnel equations. All calculated optical constants compare well the experimental ones.

Mathematical Optimization Applied to Thermal and Electrical Energy Systems

This Thesis aims at building and discussing mathematical models applications focused on Energy problems, both on the thermal and electrical side. The objective is to show how mathematical programming techniques developed within Operational Research can give useful answers in the Energy Sector, how they can provide tools to support decision making processes of Companies operating in the Energy production and distribution and how they can be successfully used to make simulations and sensitivity analyses to better understand the state of the art and convenience of a particular technology by comparing it with the available alternatives. The first part discusses the fundamental mathematical background followed by a comprehensive literature review about mathematical modelling in the Energy Sector. The second part presents mathematical models for the District Heating strategic network design and incremental network design. The objective is the selection of an optimal set of new users to be connected to an existing thermal network, maximizing revenues, minimizing infrastructure and operational costs and taking into account the main technical requirements of the real world application. Results on real and randomly generated benchmark networks are discussed with particular attention to instances characterized by big networks dimensions. The third part is devoted to the development of linear programming models for optimal battery operation in off-grid solar power schemes, with consideration of battery degradation. The key contribution of this work is the inclusion of battery degradation costs in the optimisation models. As available data on relating degradation costs to the nature of charge/discharge cycles are limited, we concentrate on investigating the sensitivity of operational patterns to the degradation cost structure. The objective is to investigate the combination of battery costs and performance at which such systems become economic. We also investigate how the system design should change when battery degradation is taken into account.

DC MICROGRID STABILIZATION THROUGH FUZZY CONTROL OF INTERLEAVED, HETEROGENEOUS STORAGE ELEMENTS

As microgrid power systems gain prevalence and renewable energy comprises greater and greater portions of distributed generation, energy storage becomes important to offset the higher variance of renewable energy sources and maximize their usefulness. One of the emerging techniques is to utilize a combination of lead-acid batteries and ultracapacitors to provide both short and long-term stabilization to microgrid systems. The different energy and power characteristics of batteries and ultracapacitors imply that they ought to be utilized in different ways. Traditional linear controls can use these energy storage systems to stabilize a power grid, but cannot effect more complex interactions. This research explores a fuzzy logic approach to microgrid stabilization. The ability of a fuzzy logic controller to regulate a dc bus in the presence of source and load fluctuations, in a manner comparable to traditional linear control systems, is explored and demonstrated. Furthermore, the expanded capabilities (such as storage balancing, self-protection, and battery optimization) of a fuzzy logic system over a traditional linear control system are shown. System simulation results are presented and validated through hardware-based experiments. These experiments confirm the capabilities of the fuzzy logic control system to regulate bus voltage, balance storage elements, optimize battery usage, and effect self-protection.

Brain electrical microstates in subjects with panic disorder

Brain electrical microstates represent spatial configurations of scalp recorded brain electrical activity and are considered to be the basic elements of stepwise processing of information in the brain. In the present study, the hypothesis of a temporo-limbic dysfunction in panic disorder (PD) was tested by investigating the topographic descriptors of brain microstates, in particular the one corresponding to the Late Positive Complex (LPC), an event-related potential (ERP) component with generators in these regions. ERPs were recorded in PD patients and matched healthy subjects during a target detection task, in a central (CC) and a lateral condition (LC). In the CC, a leftward shift of the LPC microstate positive centroid was observed in the patients with PD versus the healthy control subjects. In the LC, the topographic descriptor of the first microstate showed a rightward shift, while those of both the second and the fourth microstate, corresponding to the LPC, revealed a leftward shift in the PD patients versus the healthy control subjects. These findings indicate an overactivation of the right hemisphere networks involved in early visual processing and a hypoactivation of the right hemisphere circuits involved in LPC generators in PD. In line with this interpretation, the abnormal topography of the LPC microstate, observed in the CC, was associated with a worse performance on a test exploring right temporo-hippocampal functioning. Topographical abnormalities found for the LPC microstate in the LC were associated with a higher number of panic attacks, suggesting a pathogenetic role of the right temporo-hippocampal dysfunction in PD.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Integral energy performance characterization of semi-transparent photovoltaic elements for building integration under real operation conditions

In this paper, a methodology for the integral energy performance characterization (thermal, daylighting and electrical behavior) of semi-transparent photovoltaic modules (STPV) under real operation conditions is presented. An outdoor testing facility to analyze simultaneously thermal, luminous and electrical performance of the devices has been designed, constructed and validated. The system, composed of three independent measurement subsystems, has been operated in Madrid with four prototypes of a-Si STPV modules, each one corresponding to a specific degree of transparency. The extensive experimental campaign, continued for a whole year rotating the modules under test, has validated the reliability of the testing facility under varying environmental conditions. The thermal analyses show that both the solar protection and insulating properties of the laminated prototypes are lower than those achieved by a reference glazing whose characteristics are in accordance with the Spanish Technical Building Code. Daylighting analysis shows that STPV elements have an important lighting energy saving potential that could be exploited through their integration with strategies focused to reduce illuminance values in sunny conditions. Finally, the electrical tests show that the degree of transparency is not the most determining factor that affects the conversion efficiency.

Energy saving potential of semi-transparent photovoltaic elements for building integration

Within the building energy saving strategies, BIPV (building integrated photovoltaic systems) present a promising potential based on the close relationship existing between these multifunctional systems and the overall building energy balance. Building integration of STPV (semi-transparent photovoltaic) elements affects deeply the building energy demand since it influences the heating, cooling and lighting loads as well as the local electricity generation. This work analyses over different window-to-wall ratios the overall energy performance of five STPV elements, each element having a specific degree of transparency, in order to assess the energy saving potential compared to a conventional solar control glass compliant with the local technical standard. The prior optical characterization, focused to measure the spectral properties of the elements, was experimentally undertaken. The obtained data were used to perform simulations based on a reference office building using a package of specific software tools (DesignBuilder, EnergyPlus, PVsyst, and COMFEN) to take proper account of the STPV peculiarities. To evaluate the global energy performance of the STPV elements a new Energy Balance Index was formulated. The results show that for intermediate and large façade openings the energy saving potential provided by the STPV solutions ranges between 18% and 59% compared to the reference glass.

Aportación de la monitorización mediante redes de sensores y técnicas no invasivas para la conservación preventiva del Patrimonio

La presente tesis doctoral presenta una serie de estudios en el campo del patrimonio basados en metodologías de monitorización mediante redes de sensores y técnicas no invasivas con el objetivo de realizar nuevas aportaciones a la conservación preventiva mediante el seguimiento de los daños de deterioro o la prevención de los mismos. Las metodologías de monitorización mediante el despliegue de redes tridimensionales basadas en data loggers abordan estudios microclimáticos, de confort y energéticos a corto plazo, donde se establecen conclusiones relativas a la eficiencia energética de tres sistemas de calefacción muy utilizados en iglesias de la región centro de la Península Ibérica, abordando aspectos de afección de los mismos en el confort de los ocupantes o en el deterioro de los elementos patrimoniales o constructivos. Se desplegaron además distintas plataformas de redes de sensores inalámbricas procediendo a analizar en esta tesis cuál es la que presenta mejores resultados en el ámbito del patrimonio con el objetivo de una monitorización a largo plazo y considerando aspectos de comunicaciones, consumo y configuración de las redes. Una vez conocida la plataforma que presenta mejores resultados comparativos se muestra una metodología de estudio de la calidad de las comunicaciones en múltiples escenarios de patrimonio cultural y natural con la misma, que servirá para establecer una serie de aspectos a considerar en el despliegue de redes de sensores inalámbricas en futuros escenarios a monitorizar. Al igual que ocurre con las redes de sensores basadas en data loggers, las tareas de monitorización desarrolladas en esta tesis mediante el despliegue de las distintas plataformas inalámbricas ha permitido la detección de numerosos fenómenos de deterioro que son descritos a lo largo de la investigación y cuyo seguimiento supone una aportación a la prevención de daños en los distintos escenarios. Asimismo en el desarrollo de la tesis se realiza una aportación para la conservación preventiva mediante la monitorización con distintas técnicas no invasivas como la termografía infrarroja, las medidas de humedad superficial mediante protimeter, las técnicas de prospección de resistividad eléctrica de alta resolución o la prospección georradar. De este modo se desarrollan distintas aportaciones y conclusiones acerca de las ventajas y/o limitaciones de uso de las mismas analizando la idoneidad de aplicar cada una de ellas en distintas fases de análisis o con distintas capacidades de detección o caracterización de los daños. El estudio de imbricación de dichas técnicas ha sido desarrollado en un escenario real que presenta graves daños por humedad, habiendo sido posible la caracterización del origen de los mismos. ABSTRACT This doctoral dissertation discusses field research conducted to monitor heritage assets with sensor networks and other non-invasive techniques. The aim pursued was to contribute to conservation by tracking or preventing decay-induced damage. Monitoring methodologies based on three-dimensional data logger networks were used in short-term micro-climatic, comfort and energy studies to draw conclusions about the energy efficiency of three heating systems widely used in central Iberian churches. The impact of these systems on occupant comfort and decay of heritage or built elements was also explored. Different wireless sensor platforms were deployed and analysed to determine which delivered the best results in the context of long-term heritage monitoring from the standpoints of communications, energy demand and network architecture. A methodology was subsequently designed to study communication quality in a number of cultural and natural heritage scenarios and help establish the considerations to be borne in mind when deploying wireless sensor networks for heritage monitoring in future. As in data logger-based sensor networks, the monitoring conducted in this research with wireless platforms identified many instances of decay, described hereunder. Tracking those situations will help prevent damage in the respective scenarios. The research also contributes to preventive conservation based on non-invasive monitoring using techniques such as infrared thermography, protimeter-based surface damp measurements, high resolution electrical resistivity surveys and georadar analysis. The conclusions drawn address the advantages and drawbacks of each technique and its suitability for the various phases of analysis and capacity to detect or characterise damage. This dissertation also describes the intermeshed usage of these techniques that led to the identification of the origin of severe damp-induced damage in a real scenario.

Integración de sistemas fotovoltaicos en edificios de oficinas en bajas latitudes: estudio del balance energético aplicado a Brasil

La hipótesis que inspiró esta tesis sostiene que la integración de componentes fotovoltaicos en los cerramientos opacos y sombreamientos de huecos acristalados de edificios de oficinas en sitios ubicados en bajas latitudes, tomando como el ejemplo el caso concreto de Brasil, podría incrementar su eficiencia energética. Esta posibilidad se basa en el bloqueo de una parte significativa de la irradiación solar incidente en estos edificios, reduciendo así las cargas térmicas para la climatización y a la vez transformándola en energía eléctrica, a tal punto que se amortizan los costes de inversión en plazos aceptables a través de los ahorros en la demanda de energía. Para verificar esta hipótesis de partida se ha propuesto como objetivo general analizar la integración de elementos fotovoltaicos en cubiertas, muros opacos y sombreamiento de huecos acristalados desde la óptica del balance energético térmico y eléctrico. Inicialmente se presenta y analiza el estado del arte en los temas estudiados y la metodología de investigación, de carácter teórico basada en cálculos y simulaciones. A partir de un modelo tipo de edificio de oficinas situado en Brasil, se definen cuatro casos de estudio y una serie de parámetros, los cuales se analizan para siete latitudes ubicadas entre -1,4° y -30°, separadas las unas de las otras por aproximadamente 5°. Se presentan y discuten los resultados de más de 500 simulaciones para los siguientes conceptos: - recurso solar, desde la perspectiva de la disponibilidad de irradiación solar en distintas superficies de captación apropiadas para la integración de sistemas solares fotovoltaicos en edificaciones en bajas latitudes; - análisis de sombras, con objetivo de identificar los ángulos de sombras vertical (AVS) para protección de huecos acristalados en edificios de oficinas; - balance energético térmico, para identificar el efecto térmico del apantallamiento provocado por componentes fotovoltaicos en cubiertas, muros opacos y parasoles en ventanas en las cargas de refrigeración y consecuentemente en las demandas de energía eléctrica; - balance energético eléctrico, contrastando los resultados del balance térmico con la energía potencialmente generada en las envolventes arquitectónicas bajo estudio; - análisis económico, basado en un escenario de precios de la tecnología fotovoltaica de un mercado maduro y en la política de inyección a la red marcada por la actual normativa brasileña. Se han verificado los potenciales de ahorro económico que los sistemas activos fotovoltaicos podrían aportar, y asimismo se calculan diversos indicadores de rentabilidad financiera. En suma, esta investigación ha permitido extraer conclusiones que contribuyen al avance de la investigación y entender las condiciones que propician la viabilidad de la aplicación de componentes fotovoltaicas en las envolventes de edificios en Brasil, y hasta un cierto punto en otros países en latitudes equivalentes. ABSTRACT The hypothesis that inspired this thesis sustains that integration of photovoltaic components in the opaque envelope and shading elements of office buildings placed at low-latitude countries, using the specific case of Brazil, could increase its energy efficiency. This is possible because those components block a significant part of the incident solar irradiation, reducing its heating effect on the building and transforming its energy into electricity in such a way that the extra investments needed can be paid back in acceptable periods given the electricity bill savings they produce. In order to check this hypothesis, the main goal was to analyze the thermal and electrical performance of photovoltaic components integrated into roofs, opaque façades and window shadings. The first step is an introduction and discussion of the state of the art in the studied subjects, as well as the chosen methodology (which is theoretical), based on calculations and simulations. Starting from an office building located in Brazil, four case studies and their parameters are defined, and then analyzed, for seven cities located between latitudes -1.4° and -30°, with an approximate distance of 5° separating each one. Results of more than 500 simulations are presented and discussed for the following concepts: - Solar resource, from the perspective of irradiation availability on different surfaces for the integration of photovoltaic systems in buildings located at low latitudes; - Shading analysis, in order to determine the vertical shading angles (VSA) for protection of the glazed surfaces on office buildings; - Thermal energy balance, to identify the screening effect caused by photovoltaic components on roofs, opaque façades and window shadings on the cooling loads, and hence electricity demands; - Electric energy balance, comparing thermal energy balance with the energy potentially generated using the active skin of the buildings; - Economic analysis, based on a mature-market scenario and the current net metering rules established by the Brazilian government, to identify the potential savings these photovoltaic systems could deliver, as well as several indicators related to the return on the investment. In short, this research has led to conclusions that contribute to the further development of knowledge in this area and understanding of the conditions that favor the application of photovoltaic components in the envelope of office buildings in Brazil and, to a certain extent, in other countries at similar latitudes.

Joule heating in ferromagnetic nanostripes with a notch

The temperature in a ferromagnetic nanostripe with a notch subject to Joule heating has been studied in detail. We first performed an experimental real-time calibration of the temperature versus time as a 100 ns current pulse was injected into a Permalloy nanostripe. This calibration was repeated for different pulse amplitudes and stripe dimensions and the set of experimental curves were fitted with a computer simulation using the Fourier thermal conduction equation. The best fit of these experimental curves was obtained by including the temperature-dependent behavior of the electrical resistivity of the Permalloy and of the thermal conductivity of thesubstrate(SiO2). Notably, a nonzero interface thermal resistance between the metallic nanostripe and thesubstrate was also necessary to fit the experimental curves. We found this parameter pivotal to understand ourresults and the results from previous works. The higher current density in the notch, together with the interface thermal resistance, allows a considerable increase of the temperature in the notch, creating a large horizontal thermal gradient. This gradient, together with the high temperature in the notch and the larger current density close to the edges of the notch, can be very influential in experiments studying the current assisted domain wall motion.

Electrical investigation of p-type 4H-SiC heavily doped by ion implantation

In the last decades, an increasing interest in the research field of wide bandgap semiconductors was observed, mostly due to the progressive approaching of silicon-based devices to their theoretical limits. 4H-SiC is an example among these, and is a mature compound for applications. The main advantages offered 4H-SiC in comparison with silicon are an higher breakdown field, an higher thermal conductivity, a higher operating temperature, very high hardness and melting point, biocompatibility, but also low switching losses in high frequencies applications and lower on-resistances in unipolar devices. Then, 4H-SiC power devices offer great performance improvement; moreover, they can work in hostile environments where silicon power devices cannot function. Ion implantation technology is a key process in the fabrication of almost all kinds of SiC devices, owing to the advantage of a spatially selective doping. This work is dedicated to the electrical investigation of several differently-processed 4H-SiC ion- implanted samples, mainly through Hall effect and space charge spectroscopy experiments. It was also developed the automatic control (Labview) of several experiments. In the work, the effectiveness of high temperature post-implant thermal treatments (up to 2000°C) were studied and compared considering: (i) different methods, (ii) different temperatures and (iii) different duration of the annealing process. Preliminary p + /n and Schottky junctions were also investigated as simple test devices. 1) Heavy doping by ion implantation of single off-axis 4H-SiC layers The electrical investigation is one of the most important characterization of ion-implanted samples, which must be submitted to mandatory post-implant thermal treatment in order to both (i) recover the lattice after ion bombardment, and (ii) address the implanted impurities into lattice sites so that they can effectively act as dopants. Electrical investigation can give fundamental information on the efficiency of the electrical impurity activation. To understand the results of the research it should be noted that: (a) To realize good ohmic contacts it is necessary to obtain spatially defined highly doped regions, which must have conductivity as low as possible. (b) It has been shown that the electrical activation efficiency and the electrical conductivity increase with the annealing temperature increasing. (c) To maximize the layer conductivity, temperatures around 1700°C are generally used and implantation density high till to 10 21 cm -3 . In this work, an original approach, different from (c), is explored by the using very high annealing temperature, around 2000°C, on samples of Al + -implant concentration of the order of 10 20 cm -3 . Several Al + -implanted 4H-SiC samples, resulting of p-type conductivity, were investigated, with a nominal density varying in the range of about 1-5∙10 20 cm -3 and subjected to two different high temperature thermal treatments. One annealing method uses a radiofrequency heated furnace till to 1950°C (Conventional Annealing, CA), the other exploits a microwave field, providing a fast heating rate up to 2000°C (Micro-Wave Annealing, MWA). In this contest, mainly ion implanted p-type samples were investigated, both off-axis and on-axis <0001> semi-insulating 4H-SiC. Concerning p-type off-axis samples, a high electrical activation of implanted Al (50-70%) and a compensation ratio below 10% were estimated. In the work, the main sample processing parameters have been varied, as the implant temperature, CA annealing duration, and heating/cooling rates, and the best values assessed. MWA method leads to higher hole density and lower mobility than CA in equivalent ion implanted layers, resulting in lower resistivity, probably related to the 50°C higher annealing temperature. An optimal duration of the CA treatment was estimated in about 12-13 minutes. A RT resistivity on the lowest reported in literature for this kind of samples, has been obtained. 2) Low resistivity data: variable range hopping Notwithstanding the heavy p-type doping levels, the carrier density remained less than the critical one required for a semiconductor to metal transition. However, the high carrier densities obtained was enough to trigger a low temperature impurity band (IB) conduction. In the heaviest doped samples, such a conduction mechanism persists till to RT, without significantly prejudice the mobility values. This feature can have an interesting technological fall, because it guarantee a nearly temperature- independent carrier density, it being not affected by freeze-out effects. The usual transport mechanism occurring in the IB conduction is the nearest neighbor hopping: such a regime is effectively consistent with the resistivity temperature behavior of the lowest doped samples. In the heavier doped samples, however, a trend of the resistivity data compatible with a variable range hopping (VRH) conduction has been pointed out, here highlighted for the first time in p-type 4H-SiC. Even more: in the heaviest doped samples, and in particular, in those annealed by MWA, the temperature dependence of the resistivity data is consistent with a reduced dimensionality (2D) of the VRH conduction. In these samples, TEM investigation pointed out faulted dislocation loops in the basal plane, whose average spacing along the c-axis is comparable with the optimal length of the hops in the VRH transport. This result suggested the assignment of such a peculiar behavior to a kind of spatial confinement into a plane of the carrier hops. 3) Test device the p + -n junction In the last part of the work, the electrical properties of 4H-SiC diodes were also studied. In this case, a heavy Al + ion implantation was realized on n-type epilayers, according to the technological process applied for final devices. Good rectification properties was shown from these preliminary devices in their current-voltage characteristics. Admittance spectroscopy and deep level transient spectroscopy measurements showed the presence of electrically active defects other than the dopants ones, induced in the active region of the diodes by ion implantation. A critical comparison with the literature of these defects was performed. Preliminary to such an investigation, it was assessed the experimental set up for the admittance spectroscopy and current-voltage investigation and the automatic control of these measurements.

Filmes de óxido de zinco e nitreto de zinco depositados por magnetron sputtering com diferentes pressões de argônio, oxigênio e nitrogênio.

O óxido de zinco é um material semicondutor que apresenta alta transparência óptica no espectro visível, alta energia de ligação de éxcitons e piezoeletricidade. Por suas propriedades, ele é utilizado na área de sensores, eletrodos transparentes e dispositivos optoeletrônicos. No entanto, sua utilização ainda é limitada pela dificuldade de obtenção de condutividade tipo p, cujo principal dopante é o nitrogênio, devido à assimetria de dopagem ocasionada por defeitos intrínsecos do material, dopagem em valências diferentes das esperadas e formação de níveis de aceitadores profundos na banda proibida. A aplicação em dispositivos piezoelétricos também exige alta resistividade e ótimas propriedades cristalinas. Muitos processos de deposição estabelecidos hoje ainda utilizam altas temperaturas, o que impede sua deposição sobre superfícies ou substratos sensíveis a altas temperaturas. O objetivo deste trabalho é desenvolver técnicas de deposição de filmes de ZnO, principalmente em baixas temperaturas ( 100°C), pelo método de magnetron sputtering de rádio frequência, para avaliar a influência dos gases de processo nas características estruturais, estequiométricas, elétricas e ópticas dos filmes. Para isso, foram obtidos filmes utilizando pressão total de argônio, e pressões parciais de argônio e oxigênio e argônio e nitrogênio, utilizando alvo cerâmico de óxido de zinco ou alvo metálico de zinco. Para alvo de ZnO, filmes com condutividade tipo n foram obtidos em ambiente de argônio, em condições que geraram deficiências de oxigênio. Filmes altamente resistivos foram obtidos com a utilização de pressão parcial de oxigênio no gás de processo, em condições que resultaram em filmes estequiométricos, inclusive com condutividade tipo p. Condutividade tipo p mais alta foi observada, apenas por ponta quente, para uma amostra obtida em argônio logo após a utilização de nitrogênio na câmara de processo, que provavelmente sofreu influência da dopagem não intencional do cobre, que foi identificado como um contaminante do processo devido à estrutura da câmara. Para alvo de Zn, observou-se a formação de nitreto de zinco, que demonstrou alta capacidade de oxidação em ambiente atmosférico, e portanto, transforma-se naturalmente ao longo do tempo ou por processos de oxidação térmica em ZnO dopado com nitrogênio. Filmes de ZnO produzidos a partir de nitreto de zinco foram os únicos dos testados que apresentaram fotoluminescência característica do ZnO, mesmo para processos onde não houve aquecimento intencional.

Multifunctional cement composites strain and damage sensors applied on reinforced concrete (RC) structural elements

In this research, strain-sensing and damage-sensing functional properties of cement composites have been studied on a conventional reinforced concrete (RC) beam. Carbon nanofiber (CNFCC) and fiber (CFCC) cement composites were used as sensors on a 4 m long RC beam. Different casting conditions (in situ or attached), service location (under tension or compression) and electrical contacts (embedded or superficial) were compared. Both CNFCC and CFCC were suitable as strain sensors in reversible (elastic) sensing condition testing. CNFCC showed higher sensitivities (gage factor up to 191.8), while CFCC only reached gage factors values of 178.9 (tension) or 49.5 (compression). Furthermore, damage-sensing tests were run, increasing the applied load progressively up to the RC beam failure. In these conditions, CNFCC sensors were also strain sensitive, but no damage sensing mechanism was detected for the strain levels achieved during the tests. Hence, these cement composites could act as strain sensors, even for severe damaged structures near to their collapse.

Shape Effect of Electrochemical Chloride Extraction in Structural Reinforced Concrete Elements Using a New Cement-Based Anodic System

This article shows the research carried out by the authors focused on how the shape of structural reinforced concrete elements treated with electrochemical chloride extraction can affect the efficiency of this process. Assuming the current use of different anode systems, the present study considers the comparison of results between conventional anodes based on Ti-RuO2 wire mesh and a cement-based anodic system such as a paste of graphite-cement. Reinforced concrete elements of a meter length were molded to serve as laboratory specimens, to closely represent authentic structural supports, with circular and rectangular sections. Results confirm almost equal performances for both types of anode systems when electrochemical chloride extraction is applied to isotropic structural elements. In the case of anisotropic ones, such as rectangular sections with no uniformly distributed rebar, differences in electrical flow density were detected during the treatment. Those differences were more extreme for Ti-RuO2 mesh anode system. This particular shape effect is evidenced by obtaining the efficiencies of electrochemical chloride extraction in different points of specimens.