The microwell-mesh: A novel device and protocol for the high throughput manufacturing of cartilage microtissues

Microwell platforms are frequently described for the efficient and uniform manufacture of 3-dimensional (3D) multicellular microtissues. Multiple partial or complete medium exchanges can displace microtissues from discrete microwells, and this can result in either the loss of microtissues from culture, or microtissue amalgamation when displaced microtissues fall into common microwells. Herein we describe the first microwell platform that incorporates a mesh to retain microtissues within discrete microwells; the microwell-mesh. We show that bonding a nylon mesh with an appropriate pore size over the microwell openings allows single cells to pass through the mesh into the microwells during the seeding process, but subsequently retains assembled microtissues within discrete microwells. To demonstrate the utility of this platform, we used the microwell-mesh to manufacture hundreds of cartilage microtissues, each formed from 5 × 10(3) bone marrow-derived mesenchymal stem/stromal cells (MSC). The microwell-mesh enabled reliable microtissue retention over 21-day cultures that included multiple full medium exchanges. Cartilage-like matrix formation was more rapid and homogeneous in microtissues than in conventional large diameter control cartilage pellets formed from 2 × 10(5) MSC each. The microwell-mesh platform offers an elegant mechanism to retain microtissues in microwells, and we believe that this improvement will make this platform useful in 3D culture protocols that require multiple medium exchanges, such as those that mimic specific developmental processes or complex sequential drug exposures.

Pressure-induced first-order transition in layered crystalline semiconductor GeSe to a metallic phase

The electrical resistivity of layerd crystalline GeSe has been investigated up to a pressure of 100 kbar and down to liquid-nitrogen temperature by use of a Bridgman anvil device. A pressure-induced first-order phase transition has been observed in single-crystal GeSe near 6 GPa. The high-pressure phase is found to be quenchable and an x-ray diffraction study of the quenched material reveals that it has the face-centered-cubic structure. Resistivity measurements as a function of pressure and temperature suggest that the high-pressure phase is metallic.

Metal-insulator-semiconductor capacitors with bismuth oxide as insulator

Metal-insulator-semiconductor capacitors using aluminum Bi2O3 and silicon have been studied for varactor applications. Reactively sputtered Bi2O3 films which under suitable proportions of oxygen and argon and had high resistivity suitable for device applications showed a dielectric constant of 25. Journal of Applied Physics is copyrighted by The American Institute of Physics.

Chemically Programmed Ultrahigh Density Two-Dimensional Semiconductor Superlattice Array

Designing an ultrahigh density linear superlattice array consisting of periodic blocks of different semiconductors in the strong confinement regime via a direct synthetic route remains an unachieved challenge in nanotechnology. We report a general synthesis route for the formulation of a large-area ultrahigh density superlattice array that involves adjoining multiple units of ZnS rods by prolate US particles at the tips. A single one-dimensional wire is 300-500 nm long and consists of periodic quantum wells with a barrier width of 5 nm provided by ZnS and a well width of 1-2 nm provided by CdS, defining a superlattice structure. The synthesis route allows for tailoring of ultranarrow laserlike emissions (fwhm approximate to 125 meV) originating from strong interwell energy dispersion along with control of the width, pitch, and registry of the superlattice assembly. Such an exceptional high-density superlattice array could form the basis of ultrahigh density memories in addition to offering opportunities for technological advancement in conventional heterojunction-based device applications.

The Path to a Porous Semiconductor Multilayer

Thin films are the basis of much of recent technological advance, ranging from coatings with mechanical or optical benefits to platforms for nanoscale electronics. In the latter, semiconductors have been the norm ever since silicon became the main construction material for a multitude of electronical components. The array of characteristics of silicon-based systems can be widened by manipulating the structure of the thin films at the nanoscale - for instance, by making them porous. The different characteristics of different films can then to some extent be combined by simple superposition. Thin films can be manufactured using many different methods. One emerging field is cluster beam deposition, where aggregates of hundreds or thousands of atoms are deposited one by one to form a layer, the characteristics of which depend on the parameters of deposition. One critical parameter is deposition energy, which dictates how porous, if at all, the layer becomes. Other parameters, such as sputtering rate and aggregation conditions, have an effect on the size and consistency of the individual clusters. Understanding nanoscale processes, which cannot be observed experimentally, is fundamental to optimizing experimental techniques and inventing new possibilities for advances at this scale. Atomistic computer simulations offer a window to the world of nanometers and nanoseconds in a way unparalleled by the most accurate of microscopes. Transmission electron microscope image simulations can then bridge this gap by providing a tangible link between the simulated and the experimental. In this thesis, the entire process of cluster beam deposition is explored using molecular dynamics and image simulations. The process begins with the formation of the clusters, which is investigated for Si/Ge in an Ar atmosphere. The structure of the clusters is optimized to bring it as close to the experimental ideal as possible. Then, clusters are deposited, one by one, onto a substrate, until a sufficiently thick layer has been produced. Finally, the concept is expanded by further deposition with different parameters, resulting in multiple superimposed layers of different porosities. This work demonstrates how the aggregation of clusters is not entirely understood within the scope of the approximations used in the simulations; yet, it is also shown how the continued deposition of clusters with a varying deposition energy can lead to a novel kind of nanostructured thin film: a multielemental porous multilayer. According to theory, these new structures have characteristics that can be tailored for a variety of applications, with precision heretofore unseen in conventional multilayer manufacture.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Thin film amorphous semiconductor microwave switches

Microwave switches operating in the X band were designed and fabricated using amorphous chalcogenide semiconductors of composition GexTeyAsz. Threshold devices were shown to operate as microwave modulators at modulation frequencies of up to 100 MHz. No delay time was observed at the highest frequency although the modulation efficiency decreased above 10 MHz owing to the finite recovery time which was approximately 0.3 × 10−8s. The devices can also be used as variolossers, the insertion loss being 0.5 dB in the OFF state and increasing on switching from 5 dB at 1 mA device current to 18 dB at 100 mA.The behaviour of the threshold switches can be explained in terms of the formation of a conducting filament in the ON state with a constant current density of 2 × 104Acm−2 that is shunted by the device capacitance. The OFF state conductivity σ varies as ωn (0.5 < n < 1) which is characteristic of hopping in localized states. However, there was evidence of a decrease in n or a saturation of the conductivity at high frequencies.As a result of phase separation memory switches require no holding current in the ON state and may be used as novel latching semiconductor phase-shifters.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Controlling Light Absorption in Charge-Separating Core/Shell Semiconductor Nanocrystals

Semiconductor nanocrystals of different formulations have been extensively studied for use in thin-film photovoltaics. Materials used in such devices need to satisfy the stringent requirement of having large absorption cross sections. Hence, type-II semiconductor nanocrystals that are generally considered to be poor light absorbers have largely been ignored. In this article, we show that type-II semiconductor nanocrystals can be tailored to match the light-absorption abilities of other types of nanostructures as well as bulk semiconductors. We synthesize type-II ZnTe/CdS core/shell nanocrystals. This material is found to exhibit a tunable band gap as well as absorption cross sections that are comparable to (die. This result has significant implications for thin-film photovoltaics, where the use of type-II nanocrystals instead of pure semiconductors can improve charge separation while also providing a much needed handle to regulate device composition.

Organic device electrode fabricated by aluminum in nanopowder and bulk form and effect on device properties

Schottky barrier devices of metal/semiconductor/metal structure were fabricated using organic semiconductor polyaniline (PANI) and aluminium thin film cathode. Aluminium contacts were made by thermal evaporation technique using two different forms of metals (bulk and nanopowder). The structure and surface morphology of these films were investigated by X-ray diffraction, scanning electron microscopy, and atomic force microscopy. Grain size of the as-deposited films obtained by Scherrer's method, modified Williamson-Hall method, and SEM were found to be different. Current-voltage (I-V) characteristic of Schottky barrier device structure indicates that the calculated current density (J) for device fabricated from aluminium nanopowder is more than that from aluminium in bulk form.

Performance analysis of boron nitride embedded armchair graphene nanoribbon metal-oxide-semiconductor field effect transistor with Stone Wales defects

We study the performance of a hybrid Graphene-Boron Nitride armchair nanoribbon (a-GNR-BN) n-MOSFET at its ballistic transport limit. We consider three geometric configurations 3p, 3p + 1, and 3p + 2 of a-GNR-BN with BN atoms embedded on either side (2, 4, and 6 BN) on the GNR. Material properties like band gap, effective mass, and density of states of these H-passivated structures are evaluated using the Density Functional Theory. Using these material parameters, self-consistent Poisson-Schrodinger simulations are carried out under the Non Equilibrium Green's Function formalism to calculate the ballistic n-MOSFET device characteristics. For a hybrid nanoribbon of width similar to 5 nm, the simulated ON current is found to be in the range of 265 mu A-280 mu A with an ON/OFF ratio 7.1 x 10(6)-7.4 x 10(6) for a V-DD = 0.68 V corresponding to 10 nm technology node. We further study the impact of randomly distributed Stone Wales (SW) defects in these hybrid structures and only 2.5% degradation of ON current is observed for SW defect density of 3.18%. (C) 2014 AIP Publishing LLC.

Influence of curvature on the device physics of thin film transistors on flexible substrates

Thin film transistors (TFTs) on elastomers promise flexible electronics with stretching and bending. Recently, there have been several experimental studies reporting the behavior of TFTs under bending and buckling. In the presence of stress, the insulator capacitance is influenced due to two reasons. The first is the variation in insulator thickness depending on the Poisson ratio and strain. The second is the geometric influence of the curvature of the insulator-semiconductor interface during bending or buckling. This paper models the role of curvature on TFT performance and brings to light an elegant result wherein the TFT characteristics is dependent on the area under the capacitance-distance curve. The paper compares models with simulations and explains several experimental findings reported in literature. (C) 2014 AIP Publishing LLC.