Power line communication in motor cables of variable-speed electric drives − analysis and

Data transmission between an electric motor and a frequency converter is required in variablespeed electric drives because of sensors installed at the motor. Sensor information can be used for various useful applications to improve the system reliability and its properties. Traditionally, the communication medium is implemented by an additional cabling. However, the costs of the traditional method may be an obstacle to the wider application of data transmission between a motor and a frequency converter. In any case, a power cable is always installed between a motor and a frequency converter for power supply, and hence it may be applied as a communication medium for sensor level data. This thesis considers power line communication (PLC) in inverter-fed motor power cables. The motor cable is studied as a communication channel in the frequency band of 100 kHz−30 MHz. The communication channel and noise characteristics are described. All the individual components included in a variable-speed electric drive are presented in detail. A channel model is developed, and it is verified by measurements. A theoretical channel information capacity analysis is carried out to estimate the opportunities of a communication medium. Suitable communication and forward error correction (FEC) methods are suggested. A general method to implement a broadband and Ethernet-based communication medium between a motor and a frequency converter is proposed. A coupling interface is also developed that allows to install the communication device safely to a three-phase inverter-fed motor power cable. Practical tests are carried out, and the results are analyzed. Possible applications for the proposed method are presented. A speed feedback motor control application is verified in detail by simulations and laboratory tests because of restrictions for the delay in the feedback loop caused by PLC. Other possible applications are discussed at a more general level.

Noise Reduction Using Low Weight and Constant Weight Coding Techniques

Signalling off-chip requires significant current. As a result, a chip's power-supply current changes drastically during certain output-bus transitions. These current fluctuations cause a voltage drop between the chip and circuit board due to the parasitic inductance of the power-supply package leads. Digital designers often go to great lengths to reduce this "transmitted" noise. Cray, for instance, carefully balances output signals using a technique called differential signalling to guarantee a chip has constant output current. Transmitted-noise reduction costs Cray a factor of two in output pins and wires. Coding achieves similar results at smaller costs.

Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Direction Finding Estimators of Cyclostationary Signals in Array Processing for Microwave Power Transmission

A solar power satellite is paid attention to as a clean, inexhaustible large- scale base-load power supply. The following technology related to beam control is used: A pilot signal is sent from the power receiving site and after direction of arrival estimation the beam is directed back to the earth by same direction. A novel direction-finding algorithm based on linear prediction technique for exploiting cyclostationary statistical information (spatial and temporal) is explored. Many modulated communication signals exhibit a cyclostationarity (or periodic correlation) property, corresponding to the underlying periodicity arising from carrier frequencies or baud rates. The problem was solved by using both cyclic second-order statistics and cyclic higher-order statistics. By evaluating the corresponding cyclic statistics of the received data at certain cycle frequencies, we can extract the cyclic correlations of only signals with the same cycle frequency and null out the cyclic correlations of stationary additive noise and all other co-channel interferences with different cycle frequencies. Thus, the signal detection capability can be significantly improved. The proposed algorithms employ cyclic higher-order statistics of the array output and suppress additive Gaussian noise of unknown spectral content, even when the noise shares common cycle frequencies with the non-Gaussian signals of interest. The proposed method completely exploits temporal information (multiple lag ), and also can correctly estimate direction of arrival of desired signals by suppressing undesired signals. Our approach was generalized over direction of arrival estimation of cyclostationary coherent signals. In this paper, we propose a new approach for exploiting cyclostationarity that seems to be more advanced in comparison with the other existing direction finding algorithms.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

RF Receiver Front End for 28.5 GHz Applications on a 70 GHz F-T SiGe BiCMOS Process

This article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system-level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14 5 dB. The receiver operates from a 2 5 V power supply with a total current consumption of 31 mA.

A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing Maximum Power Point Tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 mu m CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 mu W to the load using 1712 mu W of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

Transimpedance amplifier for early detection of breast cancer

Breast cancer is the most common type of cancer worldwide. The effectiveness of its treatment depends on early stage detection, as well as on the accuracy of its diagnosis. Recently, diagnosis techniques have been submitted to relevant breakthroughs with the upcoming of Magnetic Resonance Imaging, Ultrasound Sonograms and Positron Emission Tomography (PET) scans, among others. The work presented here is focused on studying the application of a PET system to a Positron Emission Mammography (PEM) system. A PET/PEM system works under the principle that a scintillating crystal will detect a gamma-ray pulse, originated at the cancerous cells, converting it into a correspondent visible light pulse. The latter must then be converted into an electrical current pulse by means of a Photo- -Sensitive Device (PSD). After the PSD there must be a Transimpedance Amplifier (TIA) in order to convert the current pulse into a suitable output voltage, in a time period lower than 40 ns. In this Thesis, the PSD considered is a Silicon Photo-Multiplier (SiPM). The usage of this recently developed type of PSD is impracticable with the conventional TIA topologies, as it will be proven. Therefore, the usage of the Regulated Common-Gate (RCG) topology will be studied in the design of the amplifier. There will be also presented two RCG variations, comprising a noise response improvement and differential operation of the circuit. The mentioned topology will also be tested in a Radio-Frequency front-end, showing the versatility of the RCG. A study comprising a low-voltage self-biasing feedback TIA will also be shown. The proposed circuits will be simulated with standard CMOS technology (UMC 130 nm), using a 1.2 V power supply. A power consumption of 0.34 mW with a signal-to-noise ratio of 43 dB was achieved.

Switching mode power amplifier for bluetooth applications

Modern fully integrated transceivers architectures, require circuits with low area, low cost, low power, and high efficiency. A key block in modern transceivers is the power amplifier, which is deeply studied in this thesis. First, we study the implementation of a classical Class-A amplifier, describing the basic operation of an RF power amplifier, and analysing the influence of the real models of the reactive components in its operation. Secondly, the Class-E amplifier is deeply studied. The different types of implementations are reviewed and theoretical equations are derived and compared with simulations. There were selected four modes of operation for the Class-E amplifier, in order to perform the implementation of the output stage, and the subsequent comparison of results. This led to the selection of the mode with the best trade-off between efficiency and harmonics distortion, lower power consumption and higher output power. The optimal choice was a parallel circuit containing an inductor with a finite value. To complete the implementation of the PA in switching mode, a driver was implemented. The final block (output stage together with the driver) got 20 % total efficiency (PAE) transmitting 8 dBm output power to a 50 W load with a total harmonic distortion (THD) of 3 % and a total consumption of 28 mW. All implementations are designed using standard 130 nm CMOS technology. The operating frequency is 2.4 GHz and it was considered an 1.2 V DC power supply. The proposed circuit is intended to be used in a Bluetooth transmitter, however, it has a wider range of applications.

Overcoming the supply inconsistencies of tidal current energy conversion devices

The adoption of a sustainable approach to meeting the energy needs of society has recently taken on a more central and urgent place in the minds of many people. There are many reasons for this including ecological, environmental and economic concerns. One particular area where a sustainable approach has become very relevant is in the production of electricity. The contribution of renewable sources to the energy mix supplying the electricity grid is nothing new, but the focus has begun to move away from the more conventional renewable sources such as wind and hydro. The necessity of exploring new and innovative sources of renewable energy is now seen as imperative as the older forms (i.e. hydro) reach the saturation point of their possible exploitation. One such innovative source of energy currently beginning to be utilised in this regard is tidal energy. The purpose of this thesis is to isolate one specific drawback to tidal energy, which could be considered a roadblock to this energy source being a major contributor to the Irish national grid. This drawback presents itself in the inconsistent nature in which a tidal device generates energy over the course of a 24 hour period. This inconsistency of supply can result in the cycling of conventional power plants in order to even out the supply, subsequently leading to additional costs. The thesis includes a review of literature relevant to the area of tidal and other marine energy sources with an emphasis on the state of the art devices currently in development or production. The research carried out included tidal data analysis and manipulation into a model of the power generating potential at specific sites. A solution is then proposed to the drawback of inconsistency of supply, which involves the positioning of various tidal generation installations at specifically selected locations around the Irish coast. The temporal shift achieved in the power supply profiles of the individual sites by locating the installations in the correct locations, successfully produced an overall power supply profile with the smoother curve and a consistent base load energy supply. Some limitations to the method employed were also outlined, and suggestions for further improvements to the method were made.

Diseño del subsistema RF para el receptor SAR biestático en banda-C SABRINA

Este proyecto tiene como objetivo diseñar un nuevo receptor SAR biestático para el sistema SABRINA (SAR Bistatic fixed Receiver for INterferometric Applications) caracterizando el sistema que ya existía. El nuevo dispositivo deberá cumplir con las características y requisitos del escenario teniendo en cuenta la potencia recibida y el ruido de cuantificación de la tarjeta digitalizadora. Con este fin se introducen previamente conocimientos de teoría RADAR y SAR. Además, se deberá compactar al máximo el sistema para conseguir un receptor autocontenido que facilite su traslado. Para tal fin se ha incorporado a la caja del receptor un sintetizador programable que actúa de oscilador local de las cadenas de recepción y una fuente de alimentación que provee la tensión a todos los componentes activos del dispositivo. Por otra parte el proyecto ilustra las diferentes campañas de experimentos que se han realizado durante el periodo de trabajo.

FPGA-Based Control Design for Power Electronic Applications

Tehoelektoniikkalaitteella tarkoitetaan ohjaus- ja säätöjärjestelmää, jolla sähköä muokataan saatavilla olevasta muodosta haluttuun uuteen muotoon ja samalla hallitaan sähköisen tehon virtausta lähteestä käyttökohteeseen. Tämä siis eroaa signaalielektroniikasta, jossa sähköllä tyypillisesti siirretään tietoa hyödyntäen eri tiloja. Tehoelektroniikkalaitteita vertailtaessa katsotaan yleensä niiden luotettavuutta, kokoa, tehokkuutta, säätötarkkuutta ja tietysti hintaa. Tyypillisiä tehoelektroniikkalaitteita ovat taajuudenmuuttajat, UPS (Uninterruptible Power Supply) -laitteet, hitsauskoneet, induktiokuumentimet sekä erilaiset teholähteet. Perinteisesti näiden laitteiden ohjaus toteutetaan käyttäen mikroprosessoreja, ASIC- (Application Specific Integrated Circuit) tai IC (Intergrated Circuit) -piirejä sekä analogisia säätimiä. Tässä tutkimuksessa on analysoitu FPGA (Field Programmable Gate Array) -piirien soveltuvuutta tehoelektroniikan ohjaukseen. FPGA-piirien rakenne muodostuu erilaisista loogisista elementeistä ja niiden välisistä yhdysjohdoista.Loogiset elementit ovat porttipiirejä ja kiikkuja. Yhdysjohdot ja loogiset elementit ovat piirissä kiinteitä eikä koostumusta tai lukumäärää voi jälkikäteen muuttaa. Ohjelmoitavuus syntyy elementtien välisistä liitännöistä. Piirissä on lukuisia, jopa miljoonia kytkimiä, joiden asento voidaan asettaa. Siten piirin peruselementeistä voidaan muodostaa lukematon määrä erilaisia toiminnallisia kokonaisuuksia. FPGA-piirejä on pitkään käytetty kommunikointialan tuotteissa ja siksi niiden kehitys on viime vuosina ollut nopeaa. Samalla hinnat ovat pudonneet. Tästä johtuen FPGA-piiristä on tullut kiinnostava vaihtoehto myös tehoelektroniikkalaitteiden ohjaukseen. Väitöstyössä FPGA-piirien käytön soveltuvuutta on tutkittu käyttäen kahta vaativaa ja erilaista käytännön tehoelektroniikkalaitetta: taajuudenmuuttajaa ja hitsauskonetta. Molempiin testikohteisiin rakennettiin alan suomalaisten teollisuusyritysten kanssa soveltuvat prototyypit,joiden ohjauselektroniikka muutettiin FPGA-pohjaiseksi. Lisäksi kehitettiin tätä uutta tekniikkaa hyödyntävät uudentyyppiset ohjausmenetelmät. Prototyyppien toimivuutta verrattiin vastaaviin perinteisillä menetelmillä ohjattuihin kaupallisiin tuotteisiin ja havaittiin FPGA-piirien mahdollistaman rinnakkaisen laskennantuomat edut molempien tehoelektroniikkalaitteiden toimivuudessa. Työssä on myösesitetty uusia menetelmiä ja työkaluja FPGA-pohjaisen säätöjärjestelmän kehitykseen ja testaukseen. Esitetyillä menetelmillä tuotteiden kehitys saadaan mahdollisimman nopeaksi ja tehokkaaksi. Lisäksi työssä on kehitetty FPGA:n sisäinen ohjaus- ja kommunikointiväylärakenne, joka palvelee tehoelektroniikkalaitteiden ohjaussovelluksia. Uusi kommunikointirakenne edistää lisäksi jo tehtyjen osajärjestelmien uudelleen käytettävyyttä tulevissa sovelluksissa ja tuotesukupolvissa.

Teholähdepiirilevyn suunnittelu akkukäyttöiseen laitteeseen

Teholähdepiirilevyn suunnittelu etenkin kooltaan pieneen akkukäyttöiseen laitteeseen on monivaiheinen suunnitteluprosessi. Teholähdetopologioiden valinta levylle määrää heti alkuunsa kuinka vakaata jännitettä levyllä voidaan tuottaa, kuinka suuria tehoja siitä voidaan ottaa, miten paljon häiriöitä levy tuottaa ympäristöönsä ja ennen kaikkea, kun akkukäyttöisestä laitteesta on kysymys, kuinka hyvään hyötysuhteeseen sillä voidaan päästä. Suunnittelun kannalta hakkuriteholähde on teholähdetopologioista vaativin. Tässä työssä paneudutaankin tarkemmin boost-hakkuriteholähteen suunnitteluun. Pelkkä hakkurin komponenttien mitoitus ei takaa teholähteelle parasta mahdollista toimintaa, vaan myös piirilevysuunnittelulla on suuri merkitys. Akkukäyttöisen laitteen teholähdepiirilevyn suunnittelu ei rajoitu yksinomaan teholähteiden suunnitteluun vaan levy sisältää usein myös muuta oheiselektroniikkaa, yleensä ainakin laitteen käynnistyselektroniikan sekä akun latausjärjestelmän. Etenkin akun latausjärjestelmän suunnittelu saattaa muodostua hyvinkin monimutkaiseksi tehtäväksi. Tässä työssä onkin tutkittu muutaman yleisimmän akkutyypin latausmenetelmiä. Työssä suunnitellaan myös käytännössä teholähdepiirilevy akkukäyttöiseen mittalaitteeseen. Levyn toimintaa tutkitaan erinäisin mittauksin, joilla pyritään selvittämään levyn heikkoudet. Näiden heikkouksien pohjalta levystä suunnitellaan paranneltu versio. Tällekin levylle tehdään samat mittaukset kuin edelliselle versiolle, joista selviää parannusten onnistuminen.