A voltage-sensorless control method to balance the input currents of a three-wire boost rectifier under unbalanced input voltages condition

This paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectifier under unbalanced input voltage condition. The control objective is to operate the rectifier in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefficients of scaling and shifting functions are determined by two closed-loop prportional-integral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instrument's digital signal processor TMS320F24OF is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectifier under nominal and unbalanced input voltage conditions.

A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

A Novel VSI- and CSI-Fed Active-Reactive Induction Motor Drive with Sinusoidal Voltages and Currents

Till date load-commutated inverter (LCI)-fed synchronous motor drive configuration is popular in high power applications (>10 MW). The leading power factor operation of synchronous motor by excitation control offers this simple and rugged drive structure. On the contrary, LCI-fed induction motor drive is absent as it always draws lagging power factor current. Therefore, complicated commutation circuit is required to switch off thyristors for a current source inverter (CSI)-driven induction motor. It poses the major hindrance to scale up the power rating of CSI-fed induction motor drive. Anew power topology for LCI-fed induction motor drive for medium-voltage drive application is proposed. A new induction machine (active-reactive induction machine) with two sets of three-phase winding is introduced as a drive motor. The proposed power configuration ensures sinusoidal voltage and current at the motor terminals. The total drive power is shared among a thyristor-based LCI, an insulated gate bipolar transistor (IGBT)-based two-level voltage source inverter (VSI), and a three-level VSI. The benefits of SCRs and IGBTs are explored in the proposed drive. Experimental results from a prototype drive verify the basic concepts of the drive.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

Multilevel dodecagonal space-vector generation for induction motor drives by cascading three-level and two-level inverters

This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n +/- 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.

Minimization of grid current distortion in parallel-connected converters through carrier interleaving

Identical parallel-connected converters with unequal load sharing have unequal terminal voltages. The difference in terminal voltages is more pronounced in case of back-to-back connected converters, operated in power-circulation mode for the purpose of endurance tests. In this paper, a synchronous reference frame based analysis is presented to estimate the grid current distortion in interleaved, grid-connected converters with unequal terminal voltages. Influence of carrier interleaving angle on rms grid current ripple is studied theoretically as well as experimentally. Optimum interleaving angle to minimize the rms grid current ripple is investigated for different applications of parallel converters. The applications include unity power factor rectifiers, inverters for renewable energy sources, reactive power compensators, and circulating-power test set-up used for thermal testing of high-power converters. Optimum interleaving angle is shown to be a strong function of the average of the modulation indices of the two converters, irrespective of the application. The findings are verified experimentally on two parallel-connected converters, circulating reactive power of up to 150 kVA between them.

Thermoelectric properties of PbTe with encapsulated bismuth secondary phase

Lead Telluride (PbTe) with bismuth secondary phase embedded in the bulk has been prepared by matrix encapsulation technique. X-Ray Diffraction results indicated crystalline PbTe, while Rietveld analysis showed that Bi did not substitute at either Pb or Te site, which was further confirmed by Raman and X-Ray Photoelectron Spectroscopy. Scanning Electron Microscopy showed the expected presence of a secondary phase, while Energy Dispersive Spectroscopy results showed a slight deficiency of tellurium in the PbTe matrix, which might have occurred during synthesis due to higher vapor pressure of Te. Transmission Electron Microscopy results did not show any nanometer sized Bi phase. Seebeck coefficient (S) and electrical conductivity (sigma) were measured from room temperature to 725 K. A decrease in S and sigma with increasing Bi content showed an increased scattering of electrons from PbTe-Bi interfaces, along with a possible electron acceptor role of Bi secondary phase. An overall decrease in the power factor was thus observed. Thermal conductivity, measured from 400K to 725K, was smaller at starting temperature with increasing Bi concentration, and almost comparable to that of PbTe at higher temperatures, indicating a more important role of electrons as compared to phonons at PbTe-Bi interfaces. Still, a reasonable zT of 0.8 at 725K was achieved for undoped PbTe, but no improvement was found for bismuth added samples with micrometer inclusions. (C) 2013 American Institute of Physics. http://dx.doi.org/10.1063/1.4796148]

Analytical Expression for RMS DC Link Capacitor Current in a Three-Level Inverter

An analytical expression is derived for calculating the rms current through the DC link capacitor in a three level inverter. The output current of the inverter is assumed to sinusoidal. Variations in the capacitor rms current with modulation index as well as line side power factor are studied. The worst case current stress on the capacitor is determined. This is required for sizing the capacitor and is useful for predicting the capacitor losses and life. The analytical expression derived is validated through simulations and experimental results at a number of operating points.

Thermoelectric properties of a Mn substituted synthetic tetrahedrite

Tetrahedrite compounds Cu12-xMnxSb4S13 (0 <= x <= 1.8) were prepared by solid state synthesis. A detailed crystal structure analysis of Cu10.6Mn1.4Sb4S13 was performed by single crystal X-ray diffraction (XRD) at 100, 200 and 300 K confirming the noncentrosymmetric structure (space group I (4) over bar 3m) of a tetrahedrite. The large atomic displacement parameter of the Cu2 atoms was described by splitting the 12e site into a partially and randomly occupied 24g site (Cu22) in addition to the regular 12e site (Cu21), suggesting a mix of dynamic and static off-plane Cu2 atom disorder. Rietveld powder XRD pattern and electron probe microanalysis revealed that all the Mn substituted samples showed a single tetrahedrite phase. The electrical resistivity increased with increasing Mn due to substitution of Mn2+ at the Cu1+ site. The positive Seebeck coefficient for all samples indicates that the dominant carriers are holes. Even though the thermal conductivity decreased as a function of increasing Mn, the thermoelectric figure of merit ZT decreased, because the decrease of the power factor is stronger than the decrease of the thermal conductivity. The maximum ZT = 0.76 at 623 K is obtained for Cu12Sb4S13. The coefficient of thermal expansion 13.5 +/- 0.1 x 10(-6) K-1 is obtained in the temperature range from 460 K to 670 K for Cu10.2Mn1.8Sb4S13. The Debye temperature, Theta(D) = 244 K for Cu10.2Mn1.8Sb4S13, was estimated from an evaluation of the elastic properties. The effective paramagnetic moment 7.45 mu(B)/f.u. for Cu10.2Mn1.8Sb4S13 is fairly consistent with a high spin 3d(5) ground state of Mn.

Thermoelectric properties of Pb0.75-xMnxSn0.25Te alloys with variable manganese content

Lead tin telluride is one of the well-established thermoelectric materials in the temperature range 350-750 K. In the present study, Pb0.75-xMnxSn0.25Te1.00 alloys with variable manganese (Mn) content were prepared by solid state synthesis and the thermoelectric properties were studied. X-ray diffraction, (XRD) showed that the samples followed Vegard's law, indicating solid solution formation and substitution of Mn at the Pb site. Scanning Electron Microscopy (SEM) showed that the grain sizes varied from <1 mu m to more than 10 mu m and MnTe rich phase was present for higher Mn content. Seebeck coefficient, electrical resistivity and thermal conductivity were measured from room temperature to 720 K. At 300 K, large Seebeck values were obtained, possibly due to increased effective mass on Mn substitution and low carrier concentration of the samples. At higher temperatures, transition from n-type to p-type indicated the presence of thermally generated carriers. Temperature dependent electrical resistivity showed the transition from degenerate to non-degenerate behavior. For thermal conductivity, low values (similar to 1 W/m-K at 300 K) were obtained. At higher temperatures bipolar conduction was observed, in agreement with the Seebeck and resistivity data. Due to low power factor, the maximum thermoelectric figure of merit (zT) was limited to 0.23 at 329 K for the sample with lowest Mn content (x=0.03). (C) 2015 Elsevier Ltd. All rights reserved.

High thermopower and ultra low thermal conductivity in Cd-based Zintl phase compounds

By combining first principles density functional theory and electronic as well as lattice Boltzmann transport calculations, we unravel the excellent thermoelectric properties of Zintl phase compounds ACd(2)Sb(2) (where, A = Ca, Ba, Sr). The calculated electronic structures of these compounds show charge carrier pockets and heavy light bands near the band edge, which lead to a large power factor. Furthermore, we report large Gruneisen parameters and low phonon group velocity indicating essential strong anharmonicity in these compounds, which resulted in low lattice thermal conductivity. The combination of low thermal conductivity and the excellent transport properties give a high ZT value of similar to 1.4-1.9 in CaCd2Sb2 and BaCd2Sb2 at moderate p and n-type doping. Our results indicate that well optimized Cd-based Zintl phase compounds have the potential to match the performance of conventional thermoelectric materials.

In-doped multifilled n-type skutterudites with ZT=1.8

In this paper we maximize the thermoelectric (TE) figure of merit, ZT, of n-type skutterudites, (In,Sr,Ba,Yb)(y)Co4Sb12, via three different routes: (i) find the optimum fraction of In as fourth filler (ii) check the influence of powder particle, grain, and crystallite size on the TE properties and (iii) check thermal stability. Filled n-type (Sr, Ba, Yb)(y)Co4Sb12 was mixed in three different proportions with In0.4Co4Sb12, ball milled (regular or high-energy (HB) ball milling) and hot-pressed. Particle size analyses and SEM pictures of the broken surfaces of the hot pressed samples document that only HB produces uniform particles/grains with average crystallite sizes similar to 100 nm, proven by transmission electron microscopy. X-ray Rietveld refinements combined with EDX indicate that in all cases indium entered the icosahedral voids of the skutterudite. Temperature dependent physical properties of all three regularly ball-milled samples show that increasing In-content infers an increasing electrical resistivity, increasing Seebeck coefficient but a decreasing total thermal conductivity. Although ZT (823 K) is in the same range as for the sample without In, the ZT values in the whole temperature range are higher and consequently the TE-conversion efficiency, eta is at least 10% higher. Annealing the samples at 600 degrees C for three days shows minor changes in structure and thermoelectric properties, indicating TE stability. The HB sample, due to uniformly small particles, equally sized grains and crystallites, exhibits a high power factor (4.4 mW/m K-2 at 730 K) and a very low thermal conductivity leading to an outstanding high ZT = 1.8 at 823 K (eta(max) = 17.5%). (C) 2015 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved.