Volatile flavour components of baked potato flesh. A comparison of eleven potato cultivars

Tubers of eleven cultivars of potato were baked and the flavour compounds from the flesh were isolated by headspace adsorption onto Tenax and analysed by gas chromatography-mass spectrometry (GC-MS). Lipid degradation and the Maillard reaction were the main sources of flavour compounds, accounting for 22-69% and 28-77%, respectively, of the total yields. Various sulfur compounds, methoxypyrazines and terpenes were also identified at lower levels. Relative aroma impact values (RAVs) were calculated by dividing compound yields by the odour threshold value. Compounds contributing most to aroma (RAV > 10000 in at least one cultivar) were 2-isobutyl-3-methoxypyrazine, 2-isopropyl-3-methoxypyrazine, beta -damascenone, dimethyl trisulfide, decanal and 3-methylbutanal. The observed differences in yields and RAVs for compounds among cultivars would be expected to result in differences in perceived flavour.

Choice and use of standards for dynamic headspace trapping and application to the analysis of the volatiles of baked potato

When attempting to quantify the volatile components of a food isolated by dynamic headspace trapping onto an adsorbent, the analyst has to select the most appropriate compounds to use as standards and at which stage of the analysis to add them. Factors to be borne in mind include the volatility of the standard, the response of the GC detector, and whether to add the standard to the sample or to the adsorbent trap. This chapter considers the issues and describes the application of one chosen method to the quantitation of the volatile components of baked potato.

From bit level systolic arrays to HDTV processor chips

The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE.

Development of a high-throughput enzyme-linked immunosorbent assay for the routine detection of the carcinogen acrylamide in food, via rapid derivatisation pre-analysis

The spontaneous formation of the neurotoxic carcinogen acrylamide in a wide range of cooked foods has recently been discovered. These foods include bread and other bakery products, crisps, chips, breakfast cereals, and coffee. To date, the diminutive size of acrylamide (71.08Da) has prevented the development of screening immunoassays for this chemical. In this study, a polyclonal antibody capable of binding the carcinogen was produced by the synthesis of an immunogen comprising acrylamide derivatised with 3-mercaptobenzoic acid (3-MBA), and its conjugation to the carrier protein bovine thyroglobulin. Antiserum from the immunised rabbit was harvested and fully characterised. it displayed no binding affinity for acrylamide or 3-MBA but had a high affinity for 3-MBA-derivitised acrylamide. The antisera produced was utilised in the development of an ELISA based detection system for acrylamide. Spiked water samples were assayed for acrylamide content using a previously published extraction method validated for coffee, crispbread, potato, milk chocolate and potato crisp matrices. Extracted acrylamide was then subjected to a rapid 1-h derivatisation with 3-MBA, pre-analysis. The ELISA was shown to have a high specificity for acrylamide, with a limit of detection in water samples of 65.7 mu g kg(-1), i.e. potentially suitable for acrylamide detection in a wide range of food commodities. Future development of this assay will increase sensitivity further. This is the first report of an immunoassay capable of detecting the carcinogen, as its small size has necessitated current analytical detection via expensive, slower, physico-chemical techniques such as Gas or Liquid Chromatography coupled to Mass Spectrometry. (c) 2007 Elsevier B.V. All rights reserved.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.

USE OF UNIDIRECTIONAL DATA FLOW IN BIT-LEVEL SYSTOLIC ARRAY CHIPS.

We show how the architecture of two recently reported bit-level systolic array circuits - a single-bit coefficient correlator and a multibit convolver - may be modified to incorporate unidirectional data flow. This feature has advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.