On the Uncoded BER Performance Bound of the IEEE 802.16d Channel

In this letter, the performance bound of the IEEE 802.16d channel is examined analytically in order to gain an insight into its theoretical potential. Different design strategies, such as orthogonal frequency division multiplexing (OFDM) and single-carrier frequency-domain equalization (SC-FDE), time-domain decision feedback equalization (DFE), and sphere decoder (SD) techniques are discussed and compared to the theoretical bound.

Improving the ultra-low-power performance of IEEE 802.15.6 by adaptive synchronisation

In ultra-low data rate wireless sensor networks (WSNs) waking up just to listen to a beacon every superframe can be a major waste of energy. This study introduces MedMAC, a medium access protocol for ultra-low data rate WSNs that achieves significant energy efficiency through a novel synchronisation mechanism. The new draft IEEE 802.15.6 standard for body area networks includes a sub-class of applications such as medical implantable devices and long-term micro miniature sensors with ultra-low power requirements. It will be desirable for these devices to have 10 years or more of operation between battery changes, or to have average current requirements matched to energy harvesting technology. Simulation results are presented to show that the MedMAC allows nodes to maintain synchronisation to the network while sleeping through many beacons with a significant increase in energy efficiency during periods of particularly low data transfer. Results from a comparative analysis of MedMAC and IEEE 802.15.6 MAC show that MedMAC has superior efficiency with energy savings of between 25 and 87 for the presented scenarios. © 2011 The Institution of Engineering and Technology.

Software defined FFT architecture for IEEE 802.11ac

The upcoming IEEE 802.11ac standard boosts the throughput of previous IEEE 802.11n by adding wider 80 MHz and 160 MHz channels with up to 8 antennas (versus 40 MHz channel and 4 antennas in 802.11n). This necessitates new 1-8 stream 256/512-point Fast Fourier Transform (FFT) / inverse FFT (IFFT) processing with 80/160 MSample/s throughput. Although there are abundant related work, they all fail to meet the requirements of IEEE 802.11ac FFT/IFFT on point size, throughput and multiple data streams at the same time. This paper proposes the first software defined FFT/IFFT architecture as a solution. By making use of a customised soft stream processor on FPGA, we show how a software defined FFT architecture can meet all the requirements of IEEE 802.11ac with low cost and high resource efficiency. When compared with dedicated Xilinx FFT core, our implementation exhibits only one third of the resources also up to three times of resource efficiency.