Study of Multilevel Sinusoidal PWM methods for Cascaded H-Bridge Multilevel Inverters

This paper is a study of Multilevel Sinusoidal Pulse Width Modulation (MSPWM) methods; Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) on a single phase Cascaded H-Bridge Multilevel inverter. Various factors such as amplitude modulation index (Ma), frequency modulation index (M-f), phase angle between carrier and reference modulating wave (phi) have been considered for simulation. Variation in these factors and their effect on inverter performance is evaluated. Factors such as DC bus utilization, output r.m.s voltage, total harmonic distortion (%THD), dominant harmonic order, switching losses are evaluated based on simulation results.

An Open-End winding IM drive with Multilevel 12-sided Polygonal Vectors with Symmetric Triangles

Multilevel inverters with hexagonal voltage space vector structures have improved performance of induction motor drives compared to that of the two level inverters. Further reduction in the torque ripple on the motor shaft is possible by using multilevel dodecagonal (12-sided polygon) voltage space vector structures. The advantages of dodecagonal voltage space vector based PWM techniques are the complete elimination of fifth and seventh harmonics in phase voltages for the full modulation range and the extension of linear modulation range. This paper proposes an inverter circuit topology capable of generating multilevel dodecagonal voltage space vectors with symmetric triangles, by cascading two asymmetric three level inverters with isolated H-Bridges. This is made possible by proper selection of DC link voltages and the selection of resultant switching states for the inverters. In this paper, a simple PWM timing calculation method is proposed. Experimental results have also been presented in this paper to validate the proposed concept.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.

32 Gb/s multilevel modulation of an 850 nm VCSEL for next-generation datacommunication standards

An 850 nm vertical-cavity surface-emitting laser is modulated at 32 Gb/s using pulse-amplitude modulation with four levels. Transmitter predistortion generates an optimized modulation waveform, which requires a receiver bandwidth of only 15 GHz. © 2011 OSA.

10-Gbit/s transmission over 300-m standard multimode fiber using multilevel coding and 2-channel WDM

A combination of multilevel coding schemes and simple two-channel wavelength division multiplexing (WDM) at 1300 and 1550 nm was used to transmit an aggregate of 10 Gbit/s over 300 m of multimode fiber that is typical of that employed in current Local Area Networks (LANs). It was shown that this technique could be a simple solution for achieving 10 Gigabit ethernet links over installed multimode fiber building backbones.

Parallel implementation of Multilevel BDDC

In application of the Balancing Domain Decomposition by Constraints (BDDC) to a case with many substructures, solving the coarse problem exactly becomes the bottleneck which spoils scalability of the solver. However, it is straightforward for BDDC to substitute the exact solution of the coarse problem by another step of BDDC method with subdomains playing the role of elements. In this way, the algorithm of three-level BDDC method is obtained. If this approach is applied recursively, multilevel BDDC method is derived. We present a detailed description of a recently developed parallel implementation of this algorithm. The implementation is applied to an engineering problem of linear elasticity and a benchmark problem of Stokes flow in a cavity. Results by the multilevel approach are compared to those by the standard (two-level) BDDC method.

3 Gbit/s LED-based step index plastic optical fiber link using multilevel pulse amplitude modulation

Multilevel PAM is investigated for a LED-based SI-POF link. Using PAM-8, transmission at a record 3 Gbit/s is demonstrated for a maximum length of 25 m step index POF with offline post-receiver processing. © 2013 OSA.

3 Gbit/s LED-based step index plastic optical fiber link using multilevel pulse amplitude modulation

Multilevel PAM is investigated for a LED-based SI-POF link. Using PAM-8, transmission at a record 3 Gbit/s is demonstrated for a maximum length of 25 m step index POF with offline post-receiver processing. © 2013 OSA.

32 Gb/s multilevel modulation of an 850 nm VCSEL for next-generation datacommunication standards

An 850 nm vertical-cavity surface-emitting laser is modulated at 32 Gb/s using pulseamplitude modulation with four levels. Transmitter predistortion generates an optimized modulation waveform, which requires a receiver bandwidth of only 15 GHz. © OSA/ CLEO 2011.