Besov spaces and the Laplacian on fractal H-sets

Nesta tese são estudados espaços de Besov de suavidade generalizada em espaços euclidianos, numa classe de fractais designados conjuntos-h e em estruturas abstractas designadas por espaços-h. Foram obtidas caracterizações e propriedades para estes espaços de funções. Em particular, no caso de espaços de Besov em espaços euclidianos, foram obtidas caracterizações por diferenças e por decomposições em átomos não suaves, foi provada uma propriedade de homogeneidade e foram estudados multiplicadores pontuais. Para espaços de Besov em conjuntos-h foi obtida uma caracterização por decomposições em átomos não suaves e foi construído um operador extensão. Com o recurso a cartas, os resultados obtidos para estes espaços de funções em fractais foram aplicados para definir e trabalhar com espaços de Besov de suavidade generalizada em estruturas abstractas. Nesta tese foi também estudado o laplaciano fractal, considerado a actuar em espaços de Besov de suavidade generalizada em domínios que contêm um conjunto-h fractal. Foram obtidos resultados no contexto de teoria espectral para este operador e foi estudado, à custa deste operador, um problema de Dirichlet fractal no contexto de conjuntos-h.

Thick-microstructures for MPGDs: simulations and experimental studies

Cherenkov Imaging counters require large photosensitive areas, capable of single photon detection, operating at stable high gains under radioactive backgrounds while standing high rates, providing a fast response and a good time resolution, and being insensitive to magnetic fields. The development of photon detectors based in Micro Pattern Gaseous detectors (MPGDs), represent a new generation of gaseous photon detectors. In particular, gaseous detectors based on stacked Thick-Gaseous Electron Multipliers (THGEMs), or THGEM based structures, coupled to a CsI photoconverter coating, seem to fulfil the requirements imposed by Cherenkov imaging counters. This work focus on the study of the THGEM-based detectors response as function of its geometrical parameters and applied voltages and electric fields, aiming a future upgrade of the Cherenkov Imaging counter RICH-1 of the COMPASS experiment at CERN SPS. Further studies to decrease the fraction of ions that reach the photocathode (Ion Back Flow – IBF) to minimize the ageing and maximize the photoelectron extraction are performed. Experimental studies are complemented with simulation results, also perfomed in this work.

Evaluation of the economic impact of tourism expenditures in Portugal

Dissertação de Mestrado, Economia do Turismo e Desenvolvimento Regional, Faculdade de Economia, Universidade do Algarve, 2015

A low-complexity self-calibrating adaptive quadrature receiver

In this paper digital part of a self-calibrating quadrature-receiver is described, containing a digital calibration-engine. The blind source-separation-based calibration-engine eliminates the RF-impairments in real-time hence improving the receiver's performance without the need for test/pilot tones, trimming or use of power-hungry discrete components. Furthermore, an efficient time-multiplexed calibration-engine architecture is proposed and implemented on an FPGA utilising a reduced-range multiplier structure. The use of reduced-range multipliers results in substantial reduction of area as well as power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier. The performance of the calibration-engine does not depend on the modulation format or the constellation size of the received signal; hence it can be easily integrated into the digital signal processing paths of any receiver.

Design of a power-aware digital image rejection receiver

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Derivative-free optimization and filter methods to solve nonlinear constrained problems

In real optimization problems, usually the analytical expression of the objective function is not known, nor its derivatives, or they are complex. In these cases it becomes essential to use optimization methods where the calculation of the derivatives, or the verification of their existence, is not necessary: the Direct Search Methods or Derivative-free Methods are one solution. When the problem has constraints, penalty functions are often used. Unfortunately the choice of the penalty parameters is, frequently, very difficult, because most strategies for choosing it are heuristics strategies. As an alternative to penalty function appeared the filter methods. A filter algorithm introduces a function that aggregates the constrained violations and constructs a biobjective problem. In this problem the step is accepted if it either reduces the objective function or the constrained violation. This implies that the filter methods are less parameter dependent than a penalty function. In this work, we present a new direct search method, based on simplex methods, for general constrained optimization that combines the features of the simplex method and filter methods. This method does not compute or approximate any derivatives, penalty constants or Lagrange multipliers. The basic idea of simplex filter algorithm is to construct an initial simplex and use the simplex to drive the search. We illustrate the behavior of our algorithm through some examples. The proposed methods were implemented in Java.

Fiscal policy under financial stress: A threshold VAR approach

The purpose of the project is to measure the impact of fiscal policy on the Portuguese GDP and how it may vary according to the state of the financial market. A Threshold VAR model is presented in which the two regimes are found using a financial stress index that divides the economy into a situation of financial stress and financial stability.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Aversion Analysis

In this paper : a) the consumer’s problem is studied over two periods, the second one involving S states, and the consumer being endowed with S+1 incomes and having access to N financial assets; b) the consumer is then representable by a continuously differentiable system of demands, commodity demands, asset demands and desirabilities of incomes (the S+1 Lagrange multiplier of the S+1 constraints); c) the multipliers can be transformed into subjective Arrow prices; d) the effects of the various incomes on these Arrow prices decompose into a compensation effect (an Antonelli matrix) and a wealth effect; e) the Antonelli matrix has rank S-N, the dimension of incompleteness, if the consumer can financially adjust himself when facing income shocks; f) the matrix has rank S, if not; g) in the first case, the matrix represents a residual aversion; in the second case, a fundamental aversion; the difference between them is an aversion to illiquidity; this last relation corresponds to the Drèze-Modigliani decomposition (1972); h) the fundamental aversion decomposes also into an aversion to impatience and a risk aversion; i) the above decompositions span a third decomposition; if there exists a sure asset (to be defined, the usual definition being too specific), the fundamental aversion admits a three-component decomposition, an aversion to impatience, a residual aversion and an aversion to the illiquidity of risky assets; j) the formulas of the corresponding financial premiums are also presented.

On the dynamic effects of fiscal policy

Dans le sillage de la récession mondiale de 2008-09, plusieurs questions ont été soulevées dans la littérature économique sur les effets à court et à long terme de la politique budgétaire sur l’activité économique par rapport à son signe, sa taille et sa durée. Ceux-ci ont des implications importantes pour mieux comprendre les canaux de transmission et l’efficacité des politiques budgétaires, avec la politique monétaire étant poursuivi, ainsi que pour leurs retombées économiques. Cette thèse fait partie de ce regain d’intérêt de la littérature d’examiner comment les changements dans la politique budgétaire affectent l’activité économique. Elle repose alors sur trois essais: les effets macroéconomiques des chocs de dépenses publiques et des recettes fiscales, les résultats macroéconomiques de l’interaction entre les politiques budgétaire et monétaire et le lien entre la politique budgétaire et la répartition des revenus. Le premier chapitre examine les effets des chocs de politique budgétaire (chocs de dépenses publiques et chocs de recettes fiscales) sur l’économie canadienne au cours de la période 1970-2010, en s’appuyant sur la méthode d’identification des restrictions de signe développée par Mountford et Uhlig [2009]. En réponse à la récession mondiale, les autorités fiscales dans les économies avancées, dont le Canada ont généralement mis en oeuvre une approche en deux phases pour la politique budgétaire. Tout d’abord, ils ont introduit des plans de relance sans précédent pour relancer leurs économies. Par exemple, les mesures de relance au Canada, introduites à travers le Plan d’action économique du Canada, ont été projetées à 3.2 pour cent du PIB dans le budget fédéral de 2009 tandis que l’ "American Recovery and Reinvestment Act"(ARRA) a été estimé à 7 pour cent du PIB. Par la suite, ils ont mis en place des plans d’ajustement en vue de réduire la dette publique et en assurer la soutenabilité à long terme. Dans ce contexte, évaluer les effets multiplicateurs de la politique budgétaire est important en vue d’informer sur l'efficacité de telles mesures dans la relance ou non de l'activité économique. Les résultats montrent que les multiplicateurs d'impôt varient entre 0.2 et 0.5, tandis que les multiplicateurs de dépenses varient entre 0.2 et 1.1. Les multiplicateurs des dépenses ont tendance à être plus grand que les multiplicateurs des recettes fiscales au cours des deux dernières décennies. Comme implications de politique économique, ces résultats tendent à suggérer que les ajustements budgétaires par le biais de grandes réductions de dépenses publiques pourraient être plus dommageable pour l'économie que des ajustements budgétaires par la hausse des impôts. Le deuxième chapitre, co-écrit avec Constant Lonkeng Ngouana, estime les effets multiplicateurs des dépenses publiques aux Etats-Unis en fonction du cycle de la politique monétaire. Les chocs de dépenses publiques sont identifiés comme étant des erreurs de prévision du taux de croissance des dépenses publiques à partir des données d'Enquêtes des prévisionnistes professionnels et des informations contenues dans le "Greenbook". L'état de la politique monétaire est déduite à partir de la déviation du taux des fonds fédéraux du taux cible de la Réserve Fédérale, en faisant recours à une fonction lisse de transition. L'application de la méthode des «projections locales» aux données trimestrielles américaines au cours de la période 1965-2012 suggère que les effets multiplicateurs des dépenses fédérales sont sensiblement plus élevées quand la politique monétaire est accommodante que lorsqu'elle ne l'est pas. Les résultats suggèrent aussi que les dépenses fédérales peuvent stimuler ou non la consommation privée, dépendamment du degré d’accommodation de la politique monétaire. Ce dernier résultat réconcilie ainsi, sur la base d’un cadre unifié des résultats autrement contradictoires à première vue dans la littérature. Ces résultats ont d'importantes implications de politique économique. Ils suggèrent globalement que la politique budgétaire est plus efficace lorsqu'on en a le plus besoin (par exemple, lorsque le taux de chômage est élevé), si elle est soutenue par la politique monétaire. Ils ont également des implications pour la normalisation des conditions monétaires dans les pays avancés: la sortie des politiques monétaires non-conventionnelles conduirait à des multiplicateurs de dépenses fédérales beaucoup plus faibles qu'autrement, même si le niveau de chômage restait élevé. Ceci renforce la nécessité d'une calibration prudente du calendrier de sortie des politiques monétaires non-conventionnelles. Le troisième chapitre examine l'impact des mesures d'expansion et de contraction budgétaire sur la distribution des revenus dans un panel de 18 pays d'Amérique latine au cours de la période 1990-2010, avec un accent sur les deniers 40 pour cent. Il explore alors comment ces mesures fiscales ainsi que leur composition affectent la croissance des revenus des dernier 40 pour cent, la croissance de leur part de revenu ainsi que la croissance économique. Les mesures d'expansion et de contraction budgétaire sont identifiées par des périodes au cours desquels il existe une variation significative du déficit primaire corrigé des variations conjoncturelles en pourcentage du PIB. Les résultats montrent qu'en moyenne l'expansion budgétaire par la hausse des dépenses publiques est plus favorable à la croissance des revenus des moins bien-nantis que celle par la baisse des impôts. Ce résultat est principalement soutenu par la hausse des dépenses gouvernementales de consommation courante, les transferts et subventions. En outre ces mesures d’expansion budgétaire sont favorables à la réduction des inégalités car elles permettent d'améliorer la part des revenus des moins bien-nantis tout en réduisant la part des revenus des mieux-nantis de la distribution des revenus. En outre ces mesures d’expansion budgétaire sont favorables à la réduction des inégalités car elles permettent d'améliorer la part des revenus des moins bien-nantis tout en réduisant la part des revenus des mieux-nantis de la distribution des revenus. Cependant, l'expansion budgétaire pourrait soit n'avoir aucun effet sur la croissance économique ou entraver cette dernière à travers la hausse des dépenses en capital. Les résultats relatifs à la contraction budgétaire sont quelque peu mitigés. Parfois, les mesures de contraction budgétaire sont associées à une baisse de la croissance des revenus des moins bien nantis et à une hausse des inégalités, parfois l'impact de ces mesures est non significatif. Par ailleurs, aucune des mesures n’affecte de manière significative la croissance du PIB. Comme implications de politique économique, les pays avec une certaine marge de manœuvre budgétaire pourraient entamer ou continuer à mettre en œuvre des programmes de "filets de sauvetage"--par exemple les programmes de transfert monétaire conditionnel--permettant aux segments vulnérables de la population de faire face à des chocs négatifs et aussi d'améliorer leur conditions de vie. Avec un potentiel de stimuler l'emploi peu qualifié, une relance budgétaire sage par les dépenses publique courantes pourrait également jouer un rôle important pour la réduction des inégalités. Aussi, pour éviter que les dépenses en capital freinent la croissance économique, les projets d'investissements publics efficients devraient être prioritaires dans le processus d'élaboration des politiques. Ce qui passe par la mise en œuvre des projets d'investissement avec une productivité plus élevée capable de générer la croissance économique nécessaire pour réduire les inégalités.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.