Comparison of flavor compounds of potato chips fried in palmolein and silicone fluid

The importance of the frying oil as a heat-transfer medium and as a source of flavor precursors for the formation of potato chip flavor was investigated. Potato slices were fried in palmolein or silicone fluid, and the volatile flavor compounds of the resulting chips were isolated onto Tenax and analyzed by gas chromatography-mass spectrometry. Although the heat-transfer coefficients of the oils did not differ significantly, their temperature profiles during frying were different, probably due to greater turbulence on placing potato slices in palmolein, leading to more efficient heat transfer. Levels of Strecker aldehydes and sulfides in chips fried in the two media were not significantly different, but levels of pyrazines were significantly higher in palmolein-fried chips. Amounts of 2,4-decadienal were also significantly higher in palmolein-fried chips, but there was no significant difference in hexanal levels between the samples.

Evaluation of a Microfluidic Device for the Electrochemical Determination of Halide Content in Ionic Liquids

A microfluidic device designed for electrochemical studies on a microliter scale has been utilized for the examination of impurity levels in ionic liquids (ILs). Halide impurities are common following IL synthesis, and this study demonstrates the ability to quantify low concentrations of halide in a range of ILs to levels of similar to 5 ppm, even in ILs not currently measurable using other methods such as ion chromatography. To validate the mixer device, the electrochemistry of ferrocene was also examined and compared with spectroscopic and bulk electrochemistry measurements. An automated

From bit level systolic arrays to HDTV processor chips

The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE.

Quantitative mapping of aqueous microfluidic temperature with sub-degree resolution using fluorescence lifetime imaging microscopy

The use of a water-soluble, thermo-responsive polymer as a highly sensitive fluorescence-lifetime probe of microfluidic temperature is demonstrated. The fluorescence lifetime of poly(N-isopropylacrylamide) labelled with a benzofurazan fluorophore is shown to have a steep dependence on temperature around the polymer phase transition and the photophysical origin of this response is established. The use of this unusual fluorescent probe in conjunction with fluorescence lifetime imaging microscopy (FLIM) enables the spatial variation of temperature in a microfluidic device to be mapped, on the micron scale, with a resolution of less than 0.1 degrees C. This represents an increase in temperature resolution of an order of magnitude over that achieved previously by FLIM of temperature-sensitive dyes

Thermal conductivity measurement of liquids in a microfluidic device

A new microfluidic-based approach to measuring liquid thermal conductivity is developed to address the requirement in many practical applications for measurements using small (microlitre) sample size and integration into a compact device. The approach also gives the possibility of high-throughput testing. A resistance heater and temperature sensor are incorporated into a glass microfluidic chip to allow transmission and detection of a planar thermal wave crossing a thin layer of the sample. The device is designed so that heat transfer is locally one-dimensional during a short initial time period. This allows the detected temperature transient to be separated into two distinct components: a short-time, purely one-dimensional part from which sample thermal conductivity can be determined and a remaining long-time part containing the effects of three-dimensionality and of the finite size of surrounding thermal reservoirs. Identification of the one-dimensional component yields a steady temperature difference from which sample thermal conductivity can be determined. Calibration is required to give correct representation of changing heater resistance, system layer thicknesses and solid material thermal conductivities with temperature. In this preliminary study, methanol/water mixtures are measured at atmospheric pressure over the temperature range 30-50A degrees C. The results show that the device has produced a measurement accuracy of within 2.5% over the range of thermal conductivity and temperature of the tests. A relation between measurement uncertainty and the geometric and thermal properties of the system is derived and this is used to identify ways that error could be further reduced.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.

USE OF UNIDIRECTIONAL DATA FLOW IN BIT-LEVEL SYSTOLIC ARRAY CHIPS.

We show how the architecture of two recently reported bit-level systolic array circuits - a single-bit coefficient correlator and a multibit convolver - may be modified to incorporate unidirectional data flow. This feature has advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.

Automated design of DSP array processor chips

Details are presented of the DAC (DSP ASIC Compiler) silicon compiler framework. DAC allows a non-specialist to automatically design DSP ASICs and DSP ASIC cores directly form a high level specification. Typical designs take only several minutes and the resulting layouts are comparable in area and performance to handcrafted designs.