Numerical Simulation of a Low-power Hydrazine Arcjet Thruster

A modeling study is conducted to investigate the plasma flow and heat transfer characteristics of low-power (kW class) arc-heated thrusters (arcjets) with 2:1 hydrogen/nitrogen to simulate decomposed hydrazine as the propellant. The all-speed SIMPLE algorithm is employed to solve the governing equations, which take into account the effects of compressibility, the Lorentz force and Joule heating, as well as the temperature- and pressure-dependence of the gas properties. Typical computed results about the temperature, velocity and Mach number distributions within arcjet thruster are presented for the case with arc current of 9 A and inlet stagnant pressure of 3.3×105 Pa to show the flow and heat transfer characteristics. It is found that the propellant is heated mainly in the near-cathode and constrictor region, with the highest plasma temperature appearing near the cathode tip, and the flow transition from the subsonic to supersonic regime occurs within the constrictor region. The effect of gas viscosity on the plasma flow within arcjet thruster is examined by an additional numerical test using artificially reduced values of gas viscosity. The test results show that the gas viscosity appreciably affects the plasma flow and the performance of the arcjet thruster for the cases with the hydrazine or hydrogen as the propellant. The integrated axial Lorentz force in the thruster nozzle is also calculated and compared with the thrust force of the arcjet thruster. It is found that the integrated axial Lorentz force is much smaller than the thrust force for the low-power arcjet thruster. Modeling results for the NASA 1-kW class arcjet thruster with simulated hydrazine as the propellant are found to be reasonably consistent with available experimental data.

A Low Power Wide Dynamic Range Envelope Detector

We report a 75dB, 2.8mW, 100Hz-10kHz envelope detector in a 1.5mm 2.8V CMOS technology. The envelope detector performs input-dc-insensitive voltage-to-currentconverting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide- linear-range transconductor (WLR OTA) allows greater than 1.7Vpp input voltage swings. We show theoretically that this optimal performance is technology-independent for the given topology and may be improved only by spending more power. A novel circuit topology is used to perform 140nW peak detection with controllable attack and release time constants. The lower limits of envelope detection are determined by the more dominant of two effects: The first effect is caused by the inability of amplified high-frequency signals to exceed the deadzone created by exponential nonlinearities in the rectifier. The second effect is due to an output current caused by thermal noise rectification. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low power bionic implants for the deaf, hearing aids, and speech-recognition front ends. Extension of the envelope detector to higher- frequency applications is straightforward if power consumption is inc

Performance evaluation of the RPL Protocol in fixed and mobile sinks low-power and lossy networks.

Low-Power and Lossy-Network (LLN) are usually composed of static nodes, but the increase demand for mobility in mobile robotic and dynamic environment raises the question how a routing protocol for low-power and lossy-networks such as (RPL) would perform if a mobile sink is deployed. In this paper we investigate and evaluate the behaviour of the RPL protocol in fixed and mobile sink environments with respect to different network metrics such as latency, packet delivery ratio (PDR) and energy consumption. Extensive simulation using instant Contiki simulator show significant performance differences between fixed and mobile sink environments. Fixed sink LLNs performed better in terms of average power consumption, latency and packet delivery ratio. The results demonstrated also that RPL protocol is sensitive to mobility and it increases the number of isolated nodes.

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.

Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Low-power radio telemetry: the potential for remote patient monitoring

Radio-based signalling devices will play an important role in future generations of remote patient monitoring equipment, both at home and in hospital. Ultimately, it will be possible to sample vital signs frompatients, whatever their location and without them necessarily being aware that a measurement is being taken. This paper reviews currentmethods for the transmission by radio of physiological parameters over ranges of 0.3, 3 and 30 m, and describes the radiofrequency hardware required and the carrier frequencies commonly used. Future developments, including full duplex systems and the use of more advanced modulation schemes, are described. The paper concludeswith a case studyof a humantemperature telemeter built to indicateovulation. Clinical results clearly show the advantage to be had in adopting radio biotelemetry in this instance.