Rapid VLSI design of biorthogonal wavelet transform cores

A rapid design methodology for biorthogonal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture for the wavelet filters. The architecture offers efficient hardware utilization by combining the linear phase property of biorthogonal filters with decimation in a MAC based implementation. The design has been captured in VHDL and parameterized in terms of wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. The design time to produce silicon layout of a biorthogonal wavelet based system is typically less than a day. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Design of latch-based C-element

The C-element logic gate is a key component for constructing asynchronous control in silicon integrated circuits. The purpose of this reported work is to introduce a new speed-independent C-element design, which is synthesised by the asynchronous Petrify design tool to ensure it is composed of sequential digital latches rather than complex gates. The benefits are that it guarantees correct speed-independent operation, together with easy integration in modern design flows and processes. It is compared to an equivalent speed-independent complex gate C-element design generated by Petrify in a 130 nm semiconductor process.

Design and analysis of dual-rail circuits for security applications

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Rapid design of discrete orthonormal wavelet transforms using silicon IP components

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

A Coordination and Ligand Replacement Based Three-Input Colorimetric Logic Gate Sensing Platform for Melamine, Mercury Ions, and Cysteine

Discrimination of different species in various target scopes within a single sensing platform can provide many advantages such as simplicity, rapidness, and cost effectiveness. Here we design a three-input colorimetric logic gate based on the aggregation and anti-aggregation of gold nanoparticles (Au NPs) for the sensing of melamine, cysteine, and Hg2+. The concept takes advantages of the highly specific coordination and ligand replacement reactions between melamine, cysteine, Hg2+, and Au NPs. Different outputs are obtained with the combinational inputs in the logic gates, which can serve as a reference to discriminate different analytes within a single sensing platform. Furthermore, besides the intrinsic sensitivity and selectivity of Au NPs to melamine-like compounds, the “INH” gates of melamine/cysteine and melamine/Hg2+ in this logic system can be employed for sensitive and selective detections of cysteine and Hg2+, respectively.

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

A Design & Feasibility Study of the Spaced Learning Programme

Objectives There is evidence from neuroscience, cognitive psychology and educational research that the delivery of a stimulus in a spaced format (over time) rather than a massed format (all at once) leads to more effective learning. This project aimed to pilot spaced learning materials using various spacing lengths for GCSE science by exploring the feasibility of introducing spaced leaning into regular classrooms and by evaluating teacher fidelity to the materials. The spaced learning methods will then be compared with traditional science revision techniques and a programme manual will be produced. Design A feasibility study. Methods A pilot study (4 schools) was carried out to examine the feasibility and teacher fidelity to the materials, using pupil workshops and teacher interviews. A subsequent random assignment experimental study (12 schools) will involve pre and post testing of students on a science attainment measure and a post-test implementation questionnaire. Results The literature review found that longer spacing intervals between repetitions of material (>24 hours) may be optimal for long term memory formation than shorter intervals. A logic model was developed to inform the design of various programme variants for the pilot and experimental study. This paper will report qualitative data from the initial pilot study. Conclusions The paper uses this research project as an example to explain the importance of conducting pilot work and small scale experimental studies to explore the feasibility and inform the design of educational interventions, rather than prematurely moving to RCT type studies.

Metodologia de selecção de materiais em design: base de dados nacional

Desde a Pré-História que a escolha de materiais esteve relacionada com a Arte. Mais tarde, durante a Idade Moderna vai ganhando uma importância cada vez maior. Atingida que foi a Idade Contemporânea, nomeadamente após a Revolução Industrial e durante a Segunda Guerra Mundial, devido ao aumento do número de materiais disponíveis, é que se pode falar de uma verdadeira seleção de materiais. É também após a Revolução Industrial que se clarificam as relações entre a evolução dos materiais e os movimentos e correntes das Artes Plásticas. Neste contexto, estudaram-se as interligações entre o processo de design e as metodologias de seleção, assim como as diversas tipologias de ferramentas existentes para esse efeito. Deste estudo, consideradas as respetivas vantagens e limitações, foi possível identificar bases de dados essencialmente técnicas, ou ao invés, ferramentas para inspiração com muitas imagens e pouca informação sobre as propriedades dos materiais. Para completar este levantamento crítico sobre processos e ferramentas de seleção, inquiriram-se cinquenta e três profissionais que trabalhavam em diferentes gabinetes de design portugueses. As perguntas dirigidas aos designers portugueses versaram sobre problemas relacionados com a escolha de materiais, abrangendo o tipo de matériasprimas empregues, processos utilizados e a qualidade da informação obtida. Na sequência deste estudo, verificou-se a existência de diversas lacunas relativamente aos meios disponíveis, rotinas de seleção, qualidade da informação existente e metodologias utilizadas. Foi neste contexto que se iniciou o projeto de criação de uma nova metodologia suportada por uma ferramenta digital. Os principais aspetos inovadores são: uma melhor interligação entre a metodologia de design e o processo de seleção de materiais e a sua sincronização; a informação necessária em cada etapa e o destaque dos fatores catalisadores da seleção de materiais. Outro elemento inovador foi a conjugação de três formas deferentes de seleção de materiais numa só ferramenta (a geral, a visual e a específica) e a hipótese de aceder a diferentes graus de informação. A metodologia, no contexto dos recursos disponíveis, foi materializada sob a forma de ferramenta digital (ptmaterials.com). O protótipo foi aferido com testes de usabilidade de cariz heurístico, com a participação de dezanove utilizadores. Foram detetadas diversas falhas de interação que condicionaram a liberdade e o controlo da navegação no seio da interface. Os utilizadores também mencionaram a existência de lacunas na prevenção de erros e a ligação do sistema à lógica habitual de outras aplicações já existentes. No entanto, também constituiu um estímulo a circunstância da maioria dos designers avaliarem o sistema como eficaz, eficiente, satisfatório e confirmarem o interesse da existência dos três tipos de seleção. Posteriormente, ao analisar os restantes resultados dos testes de usabilidade, também foram evidenciadas as vantagens dos diferentes tipos de informação disponibilizada e a utilidade de uma ferramenta desta natureza para a Indústria e Economia Nacionais. Esta ferramenta é apenas um ponto de partida, existindo espaço para melhorar a proposta, apesar da concretização de uma ferramenta digital ser um trabalho de grande complexidade. Não obstante se tratar de um protótipo, esta ferramenta está adequada aos dias de hoje e é passível de evoluir no futuro, tendo também a possibilidade de vir a ser preferencialmente utilizada por outros países de língua portuguesa.

Co-production and co-creation using self-service technology: the application of service-dominant logic

Research on how customers engage in the co-creation processes envisaged by the Servicedominant logic paradigm is currently limited and even less work has been published on frameworks for organizations to manage the co-creation process. This conceptual paper examines a particular aspect of co-creation: co-production as a result of the application of self-service technology (SST). We propose a conceptual framework for co-production, which emphasizes the need to understand productivity from the point of view of the customer, and demonstrate how this can be applied in both consumer (b2c) and interorganizational(b2b) contexts. We conclude that service organizations might benefit from clearly identifying co-production with task-performance, and co-creation with the valueattributing aspects of the customer service experience. Both aspects generate a range of design and management challenges for suppliers particularly the need to understand the cocreation process 'outputs' desired by customers and the full costs of moving away from person to person interaction.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

An Interactive Theorem Prover for First-Order Dynamic Logic

Dynamic logic is an extension of modal logic originally intended for reasoning about computer programs. The method of proving correctness of properties of a computer program using the well-known Hoare Logic can be implemented by utilizing the robustness of dynamic logic. For a very broad range of languages and applications in program veri cation, a theorem prover named KIV (Karlsruhe Interactive Veri er) Theorem Prover has already been developed. But a high degree of automation and its complexity make it di cult to use it for educational purposes. My research work is motivated towards the design and implementation of a similar interactive theorem prover with educational use as its main design criteria. As the key purpose of this system is to serve as an educational tool, it is a self-explanatory system that explains every step of creating a derivation, i.e., proving a theorem. This deductive system is implemented in the platform-independent programming language Java. In addition, a very popular combination of a lexical analyzer generator, JFlex, and the parser generator BYacc/J for parsing formulas and programs has been used.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Automated synthesis of delay-reduced Reed-Muller universal logic module networks

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.