Component integration strategies in metamorphic 4-junction III-V concentrator solar cells

Progressing beyond 3-junction inverted-metamorphic multijunction solar cells grown on GaAs substrates, to 4-junction devices, requires the development of high quality metamorphic 0.7 eV GaInAs solar cells. Once accomplished, the integration of this subcell into a full, Monolithic, series connected, 4J-IMM structure demands the development of a metamorphic tunnel junction lattice matched to the 1eV GaInAs subcell. Moreover, the 0.7 eV junction adds about 2 hours of growth time to the structure, implying a heavier annealing of the subcells and tunnel junctions grown first. The final 4J structure is above 20 Pm thick, with about half of this thickness used by the metamorphic buffers required to change the lattice constant throughout the structure. Thinning of these buffers would help reduce the total thickness of the 4J structure to decrease its growth cost and the annealing time. These three topics: development of a metamorphic tunnel junction for the 4th junction, analysis of the annealing, and thinning of the structure, are tackled in this work. The results presented show the successful implementation of an antimonide-based tunnel junction for the 4th junction and of pathways to mitigate the impact of annealing and reduce the thickness of the metamorphic buffers.

Implications of redesigned, high-radiative-efficiency GaInP junctions on III-V multijunction concentrator solar cells

Nonradiative recombination in inverted GaInP junctions is dramatically reduced using a rear-heterojunction design rather than the more traditional thin-emitter homojunction design. When this GaInP junction design is included in inverted multijunction solar cells, the high radiative efficiency translates into both higher subcell voltage and high luminescence coupling to underlying subcells, both of which contribute to improved performance. Subcell voltages within two and four junction devices are measured by electroluminescence and the internal radiative efficiency is quantified as a function of recombination current using optical modeling. The performance of these concentrator multijunction devices is compared with the Shockley–Queisser detailed-balance radiative limit, as well as an internal radiative limit, which considers the effects of the actual optical environment in which a perfect junction may exist.

Theory of ferromagnetism in planar heterostructures of (Mn,III)-V semiconductors

A density-functional theory of ferromagnetism in heterostructures of compound semiconductors doped with magnetic impurities is presented. The variable functions in the density-functional theory are the charge and spin densities of the itinerant carriers and the charge and localized spins of the impurities. The theory is applied to study the Curie temperature of planar heterostructures of III-V semiconductors doped with manganese atoms. The mean-field, virtual-crystal and effective-mass approximations are adopted to calculate the electronic structure, including the spin-orbit interaction, and the magnetic susceptibilities, leading to the Curie temperature. By means of these results, we attempt to understand the observed dependence of the Curie temperature of planar δ-doped ferromagnetic structures on variation of their properties. We predict a large increase of the Curie temperature by additional confinement of the holes in a δ-doped layer of Mn by a quantum well.

Petri Artedi renovati pars I. et II. [III-V] : i.e. bibliotheca et philosophia ichthyologica / cura Iohannis Iulii Walbaumii.

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Petri Artedi renovati pars I. et II. [III-V] : i.e. bibliotheca et philosophia ichthyologica / cura Iohannis Iulii Walbaumii.

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[Codicis Domini Iustiniani Sacratissimi Principis PP. Augusti repetitae praelectionis liber III [-V] /

Mode of access: Internet.

Piezo force microscopy and peakforce tuna measurements of III-V semiconductor nanowires

GaN, InP and GaAs nanowires were investigated for piezoelectric response. Nanowires and structures based on them can find wide applications in areas purposes such as nanogenarators, nanodrives, Solar cells and other perspective areas. Experemental measurements were carried out on AFM Bruker multimode 8 and data was handled with Nanoscope software. AFM techniques permitted not only to visualize the surface topography, but also to show distribution of piezoresponse and allowed to calculate its properties. The calculated values are in the same range as published by other authors.

Growth and Characterization of III-V Semiconductor Materials for MOCVD Reactor Qualification and Process Control

Metalorganic chemical vapor deposition is examined as a technique for growing compound semiconductor structures. Material analysis techniques for characterizing the quality and properties of compound semiconductor material are explained and data from recent commissioning work on a newly installed reactor at the University of Illinois is presented.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Design of Nanophotonic Antireflection Coatings for III-V Thin-Film Photovoltaics

Thin-film photovoltaics have provided a critical design avenue to help decrease the overall cost of solar power. However, a major drawback of thin-film solar cell technology is decreased optical absorption, making compact, high-quality antireflection coatings of critical importance to ensure that all available light enters the cell. In this thesis, we describe high efficiency thin-film InP and GaAs solar cells that utilize a periodic array of nanocylinders as antireflection coatings. We use coupled optical and electrical simulations to find that these nanophotonic structures reduce the solar-weighted average reflectivity of InP and GaAs solar cells to around 1.3 %, outperforming the best double-layer antireflection coatings. The coupling between Mie scattering resonances and thin-film interference effects accurately describes the optical enhancement provided by the nanocylinders. The spectrally resolved reflectivity and J-V characteristics of the devices under AM1.5G solar illumination are determined via the coupled optical and electrical simulations, resulting in predicted power conversion efficiencies > 23 %. We conclude that the nanostructured coatings reduce reflection without negatively affecting the electronic properties of the InP and GaAs solar cells by separating the nanostructured optical components from the active layer of the device.

Influence of V/III ratio on the structural and photoluminescence properties of In0.52AlAs/In0.53GaAs metamorphic high electron mobility transistor grown by molecular beam epitaxy

A series of metamorphic high electron mobility transistors (MMHEMTs) with different V/III flux ratios are grown on GaAs (001) substrates by molecular beam epitaxy (XIBE). The samples are analysed by using atomic force microscopy (AFM), Hall measurement, and low temperature photoluminescence (PL). The optimum V/III ratio in a range from 15 to 60 for the growth of MMHEMTs is found to be around 40. At this ratio, the root mean square (RMS) roughness of the material is only 2.02 nm; a room-temperature mobility and a sheet electron density are obtained to be 10610.0cm(2)/(V.s) and 3.26 x 10(12)cm(-2) respectively. These results are equivalent to those obtained for the same structure grown on InP substrate. There are two peaks in the PL spectrum of the structure, corresponding to two sub-energy levels of the In0.53Ga0.47 As quantum well. It is found that the photoluminescence intensities of the two peaks vary with the V/III ratio, for which the reasons are discussed.