Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Characteristics of j.f.e.t.s. taking the separation of gate electrode from the source and drain electrodes into account

The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

Measurement of probability-distribution functions sensitive technique for the study of conduction phenomena in liquid dielectrics

The paper outlines a technique for sensitive measurement of conduction phenomena in liquid dielectrics. The special features of this technique are the simplicity of the electrical system, the inexpensive instrumentation and the high accuracy. Detection, separation and analysis of a random function of current that is superimposed on the prebreakdown direct current forms the basis of this investigation. In this case, prebreakdown direct current is the output data of a test cell with large electrodes immersed in a liquid medium subjected to high direct voltages. Measurement of the probability-distribution function of a random fluctuating component of current provides a method that gives insight into the mechanism of conduction in a liquid medium subjected to high voltages and the processes that are responsible for the existence of the fluctuating component of the current.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

A comparative study of erbium oxide and gadolinium oxide high-k dielectric thin films grown by low-pressure metalorganic chemical vapour deposition (MOCVD) using beta-Diketonates as precursors

In this paper, a comparative study of thin films of Er2O3 and Gd2O3 grown on n-type Si(100) by low-pressure metalorganic chemical vapour deposition (MOCVD) under the identical conditions has been presented. beta-Diketonate complex of rate earth metals was used as precursor. Description on the evolution of the morphology, structure, optical, and electrical characteristics of films with respect to growth parameters and post-deposition annealing process has been presented. As-gown Gd2O3 films grow with <111> texture, whereas the texture of Er2O3 films strongly depends on the growth temperature (either <100> or <111>). Compositional analysis reveals that the Gd2O3 films grown at or above 500degreesC are carbon free whereas Er2O3 films at upto 525degreesC show the presence of heteroatoms and Er2O3 films grown above 525degreesC are carbon five. The effective dielectric constant is in the range of 7-24, while the fixed charge density is in the range - 10(11) to 10(10) CM-2 as extracted from the C-V characteristics. DC I-V study was carried out to examine the leakage behaviour of films. It reveals that the as-grown Gd2O3 film was very leakey in nature. Annealing of the films in oxidizing ambient for a period of 20 min results in a drastic improvement in the leakage behaviour. The presence of heteroatoms (such as carbon) and their effect on the properties of films are discussed.

Enhanced photoluminescence of Gd2O3:Eu3+ nanophosphors with alkali (M = Li+, Na+, K+) metal ion co-doping

Gd1.95Eu0.4M0.01O3 (M = Li+ Na+ K+) nanophosphors have been synthesized by a low temperature solution combustion (LSC) method. Powder X-ray diffraction pattern (PXRD), scanning electron microscopy (SEM), UV-vis and photoluminescence (PL) measurements were carried out to characterize their structural and luminescent properties. The excitation and emission spectra indicated that the phosphor could be well excited by UV light (243 nm) and emit red light about 612 nm. The effect of alkali co-dopant on PL properties has been examined. The results showed that incorporation of Li+, Na+ and K+ in to Gd2O3:Eu3+ phosphor would lead to a remarkable increase of photoluminescence. The PL intensity of Gd2O3:Eu3+ phosphor was improved evidently by co-doping with Li+ ions whose radius is less than that of Gd3+ and hardly with Na+, K+ whose radius is larger than that of Gd3+. The effect of co-dopants on enhanced luminescence was mainly regarded as the result of a suitable local distortion of crystal field surrounding the Eu3+ activator. These results will play an important role in seeking some more effective co-dopants. (C) 2011 Published by Elsevier B.V.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Synthesis, characterization, thermo- and photoluminescence properties of Bi3+ co-doped Gd2O3:Eu3+ nanophosphors

Gd2O3:Eu3+ (4 mol%) co-doped with Bi3+ (Bi = 0, 1, 3, 5, 7, 9 and 11 mol%) ions were synthesized by a low-temperature solution combustion method. The powders were calcined at 800A degrees C and were characterized by powder X-ray diffraction (PXRD), transmission electron microscopy (TEM), Fourier transform infrared and UV-Vis spectroscopy. The PXRD profiles confirm that the calcined products were in monoclinic with little cubic phases. The particle sizes were estimated using Scherrer's method and Williamson-Hall plots and are found to be in the ranges 40-60 nm and 30-80 nm, respectively. The results are in good agreement with TEM results. The photoluminescence spectra of the synthesized phosphors excited with 230 nm show emission peaks at similar to 590, 612 and 625 nm, which are due to the transitions D-5(0)-> F-7(0), D-5(0)-> F-7(2) and D-5(0)-> F-7(3) of Eu3+, respectively. It is observed that a significant quenching of Eu3+ emission was observed under 230 nm excitation when Bi3+ was co-doped. On the other hand, upon 350 nm excitation, the luminescent intensity of Eu3+ ions was enhanced by incorporation of Bi3+ (5 mol%) ions. The introduction of Bi3+ ions broadened the excitation band of Eu3+ of which a new strong band occurred ranging from 320 to 380 nm. This has been attributed to the 6s(2)-> 6s6p transition of Bi3+ ions, implying a very efficient energy transfer from Bi3+ ions to Eu3+ ions. The gamma radiation response of Gd2O3:Eu3+ exhibited a dosimetrically useful glow peak at 380A degrees C. Using thermoluminescence glow peaks, the trap parameters have been evaluated and discussed. The observed emission characteristics and energy transfer indicate that Gd2O3:Eu3+, Bi3+ phosphors have promising applications in solid-state lighting.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.