Detection of cardiac arrest using a simplified frequency analysis of the impedance cardiogram recorded from defibrillator pads

An algorithm based only on the impedance cardiogram (ICG) recorded through two defibrillation pads, using the strongest frequency component and amplitude, incorporated into a defibrillator could determine circulatory arrest and reduce delays in starting cardiopulmonary resuscitation (CPR). Frequency analysis of the ICG signal is carried out by integer filters on a sample by sample basis. They are simpler, lighter and more versatile when compared to the FFT. This alternative approach, although less accurate, is preferred due to the limited processing capacity of devices that could compromise real time usability of the FFT. These two techniques were compared across a data set comprising 13 cases of cardiac arrest and 6 normal controls. The best filters were refined on this training set and an algorithm for the detection of cardiac arrest was trained on a wider data set. The algorithm was finally tested on a validation set. The ICG was recorded in 132 cardiac arrest patients (53 training, 79 validation) and 97 controls (47 training, 50 validation): the diagnostic algorithm indicated cardiac arrest with a sensitivity of 81.1% (77.6-84.3) and specificity of 97.1% (96.7-97.4) for the validation set (95% confidence intervals). Automated defibrillators with integrated ICG analysis have the potential to improve emergency care by lay persons enabling more rapid and appropriate initiation of CPR and when combined with ECG analysis they could improve on the detection of cardiac arrest.

Inter-Area Power Oscillation Frequency Mode with Wind Turbine Generator in Irish Power System using PMU Data

Two case studies are presented in this paper to demonstrate the impact of different power system operation conditions on the power oscillation frequency modes in the Irish power system. A simplified 2 area equivalent of the Irish power system has been used in this paper, where area 1 represents the Republic of Ireland power system and area 2 represents the Northern Ireland power system.

The potential power oscillation frequency modes on the interconnector during different operation conditions have been analysed in this paper. The main objective of this paper is to analyse the influence of different operation conditions involving wind turbine generator (WTG) penetration on power oscillation frequency modes using phasor measurement unit (PMU) data.

Fast Fourier transform (FFT) analysis was performed to identify the frequency oscillation mode while correlation coefficient analysis was used to determine the source of the frequency oscillation. The results show that WTG, particularly fixed speed induction generation (FSIG), gives significant contribution to inter-area power oscillation frequency modes during high WTG operation.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

High-Speed Fully Homomorphic Encryption Over the Integers

A fully homomorphic encryption (FHE) scheme is envisioned as a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrary evaluation of a ciphertext without revealing the plaintext. However, existing FHE implementations remain impractical due to very high time and resource costs. To the authors’ knowledge, this paper presents the first hardware implementation of a full encryption primitive for FHE over the integers using FPGA technology. A large-integer multiplier architecture utilising Integer-FFT multiplication is proposed, and a large-integer Barrett modular reduction module is designed incorporating the proposed multiplier. The encryption primitive used in the integer-based FHE scheme is designed employing the proposed multiplier and modular reduction modules. The designs are verified using the Xilinx Virtex-7 FPGA platform. Experimental results show that a speed improvement factor of up to 44 is achievable for the hardware implementation of the FHE encryption scheme when compared to its corresponding software implementation. Moreover, performance analysis shows further speed improvements of the integer-based FHE encryption primitives may still be possible, for example through further optimisations or by targeting an ASIC platform.

Research Protocol: A Randomized Controlled Trial of Functional Family Therapy: An Early Intervention Foundation (EIF) Partnership between Croydon Council and Queen's University Belfast

The paper presents a protocol for ‘A Randomized Controlled Trial of Functional Family Therapy (FFT): An Early Intervention Foundation (EIF) Partnership between Croydon Council and Queen's University Belfast’. The protocol describes a trial that uses FFT as an alternative intervention to current use of the youth justice system and local authority care with the aim of reducing crime/recidivism in young people referred to Croydon Council. The trial will take place over a period of 36 months and will involve up to 154 families. Croydon Council will employ a team of five Functional Family Therapists who will work with families to promote effective outcomes. The Centre for Effective Education at Queen’s University Belfast will act as independent evaluators of outcomes for families and young people. The work is supported from the United Kingdom Economic & Social Research Council/Early Intervention Foundation Grant Number ES/M006921/1.

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

Estudo da maquinabilidade das ligas Ti-6Al-4V e Co-28Cr-6Mo na fresagem de dispositivos biomédicos

Os estudos de maquinabilidade de biomateriais e outros materiais aplicados na área médica são extensos. Todavia, muitos destes estudos recorrem a modelos de geometria regular e operações elementares de maquinagem. Relativamente a estas, os estudos académicos atualmente disponíveis mostram que a tecnologia preferencial é o torneamento, opção que se fundamenta na simplicidade de análise (corte ortogonal). Saliente-se ainda que, neste contexto, a liga de titânio Ti-6Al-4V constitui o biomaterial mais utilizado. Numa perspetiva complementar, refira-se que as publicações científicas evidenciam que a informação disponível sobre a fresagem Ti-6Al-4V não é muito extensa e a do Co-28Cr-6Mo é quase inexistente. A presente dissertação enquadra-se neste domínio e representa mais uma contribuição para o estudo da maquinabilidade das ligas de Titânio e de crómio-cobalto. A aplicação de operações de maquinagem complexas, através do recurso a programas informáticos de fabrico assistido por computador (CAM), em geometrias complexas, como é o caso das próteses femorais anatómicas, e o estudo comparativo da maquinabilidade das ligas Co-28Cr-6Mo e Ti-6Al-4V, constituem os objetivos fundamentais deste trabalho de doutoramento. Neste trabalho aborda-se a problemática da maquinabilidade das ligas metálicas usadas nos implantes ortopédicos, nomeadamente as ligas de titânio, de crómiocobalto e os aços Inoxidáveis. Efetua-se ainda um estudo da maquinagem de uma prótese femoral com uma forma geométrica complexa, onde as operações de corte foram geradas recorrendo às tecnologias de fabrico assistido por computador (CAD/CAM). Posteriormente, procedeu-se ao estudo da maquinabilidade das duas ligas usadas neste trabalho, dando uma atenção particular à determinação das forças de corte para diferentes velocidades de corte. Para além da monitorização da evolução da força de corte, o desgaste das ferramentas, a dureza e a rugosidade foram avaliadas, em função da velocidade de corte imposta. Por fim, com base nas estratégias de maquinagem adotadas, analisa-se a maquinabilidade e selecionam-se os parâmetros de corte mais favoráveis para as ligas de Titânio e Crómio-cobalto. Os resultados obtidos mostram que a liga de crómio-cobalto induz maior valor de força de corte do que a liga de titânio. Observa-se um aumento progressivo das forças de corte quando a velocidade de corte aumenta, até atingir o valor máximo para a velocidade de corte de 80m/min, após a qual, a força de corte tende a diminuir. Apesar do fabricante das ferramentas recomendar a velocidade de corte de 50 m/min para ambos os materiais, conclui-se que a velocidade de corte de 65 m/min induz o mesmo desgaste na ferramenta de corte no caso da liga de titânio, e menor desgaste no caso da liga de crómio-cobalto.

IB-DFE receiver techniques for CP-assisted block transmission within DS-CDMA and MC-CDMA systems

MC-CDMA (MultiCarrier Code Division Multiple Access), currently regarded as a promissing multiple access scheme for broadband communications, is known to combine the advantages of an OFDM-based (Orthogonal Frequency Division Multiplexing), CP-assisted (Cyclic Prefix) block transmission with those of CDMA systems. Recently, it was recognised that DS-CDMA (Direct Sequence) implementations can also take advantage of the beneficts of the CP-assisted block transmission approach, therefore enabling an efficient use of FFT-based (Fast Fourier Transform), chip level FDE (Frequency- Domain Equalisation) techniques. In this paper we consider the use of IB-DFE (Iterative Block Decision Feedback Equalisation) FDE techniques within both CP-assisted MC-CDMA systems with frequency-domain spreading and DS-CDMA systems. Our simulation results show that an IB-DFE receiver with moderate complexity is suitable in both cases, with excellent performances that can be close to the single-code matched filter bound (especially for the CP-assisted DSCDMA alternative), even with full code usage.

Joint turbo equalization and cancelation of nonlinear distortion effects in MC-CDMA signals

In this paper, we consider low-PMEPR (Peak-to-Mean Envelope Power Ratio) MC-CDMA (Multicarrier Coded Division Multiple Access) schemes. We develop frequencydomain turbo equalizers combined with an iterative estimation and cancellation of nonlinear distortion effects. Our receivers have relatively low complexity, since they allow FFT-based (Fast Fourier Transform) implementations. The proposed turbo receivers allow significant performance improvements at low and moderate SNR (Signal-to-Noise Ratio), even when a low-PMEPR MC-CDMA transmission is intended.

An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute a 256-point complex FFT in 102.4 μs excluding data input and output processes.

Análise por ultra-sons no controlo de condição

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Sistema de detecção e diagnóstico de falhas em geradores de indução duplamente alimentados

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Immersioultraäänitutkimuksen kehittäminen

Teräksenvalmistajilta edellytetään jatkuvasti panostusta laadun ja laadunvarmistuksen kehittämiseen. Teräksen laatu ja puhtaus korostuvat varsinkin silloin, kun terästä käytetään vaativiin käyttökohteisiin, kuten autoteollisuuden tarpeisiin. Ultraäänitarkastusmenetelmää käytetään laadun-varmistuksessa teräksen sisävikojen etsimiseen. Ultraäänitarkastuksessa lähetetään suuritaajuuksista ääntä kappaleeseen. Ääni etenee materiaalissa ja heijastuu erilaisista epäjatkuvuuskohdista. Luotaimeen palaavaa ääntä analysoimalla saadaan tietoa teräksestä ja sen sisävioista. Ultraäänitarkastuksen ongelmana on vian tyypin määrittäminen hankaluus sekä herkkyys tutkittavan materiaalin aineominaisuuksille. Työn tavoitteena oli immersioultraäänitarkastuksen kehittäminen sovellettuna teräksenvalmistajan tarpeisiin. Materiaalin aineominaisuuksista tutkittiin seostuksen vaikutusta. Teräslajit tarkastettiin valssitilaisena, karkaistuna ja normalisoituna. Lisäksi tutkittiin kappaleen pinnankarheuden ja -muodon vaikutusta tarkastukseen. Vikatyyppien tunnistamisen mahdollisuuksia ultra-äänitarkastuksessa selvitettiin käyttäen FFT- taajuusanalyysiä. Erilailla lämpökäsitellyillä teräslajeilla näytti eniten tuloksiin vaikuttavan terästen raekoko. Valssitilaisilla teräksillä raekoko on suuri, jolloin ultraääni vaimenee voimakkaasti teräksessä. Huomattavaa kuitenkin oli, että mikäli lämpö-käsittelyillä ei teräksen raekokoa saada juuri pienennettyä, ei myöskään vaimeneminen vähene. Tämän vuoksi lämpökäsittely ei välttämättä ole aina tarpeellinen valmisteltaessa ultraääninäytteitä. Fourier’n taajuusanalyysissä huomattiin olevan eroavaisuuksia verrattaessa huokosista ja sulkeumista palaavien kaikujen taajuusspektrejä. Näiden tulosten perusteella näyttäisi olevan mahdollista käyttää FFT- menetelmää ultraääni-tarkastuksessa vikojen luokitteluun.