Sistema embarcado para suporte ao diagnóstico de microcalcificações em mamografias digitais

Pós-graduação em Engenharia Elétrica - FEIS

Um modelo de avaliação integrada para análise de incertezas em programas governamentais: um estudo da educação a distância no Estado do Pará

A tarefa de projetar um sistema de EAD (SEAD) não é fácil, devido ao número de componentes (estudantes, corpo docente, administração, infra-estrutura, etc.), a complexidade do processo, as diferentes visões e abordagens quanto à sua eficácia, os valores em disputa, os interesses em jogo e as decisões urgentes. O Estado do Pará possui experiências de sucesso nesta modalidade em todos os níveis de ensino. Porém, ainda existem dificuldades, obstáculos, problemas e incertezas a serem enfrentados. Neste sentido, o objetivo da pesquisa foi criar um modelo analítico para identificar e interpretar as incertezas presentes na utilização da EAD pelo sistema educacional do Pará e detectar as atitudes dos atores envolvidos e interessados no processo, contribuindo com critérios e estratégias que podem ser utilizadas para decidir, sob condições de incerteza, sobre a implementação de SEADs e sua operacionalização. Para isso a pesquisa tomou como base a metodologia da Avaliação Integrada (AI), na perspectiva pluralista, sendo realizada em vários momentos, os quais incluiram: ampla pesquisa bibliográfica; sondagem do encaminhamento da EAD no Pará; o uso do método de inquerito delphi para instigar o consenso sobre as incertezas mais relevantes; utilização da Teoria Cultural para subsidiar a identificação da orientação cultural dos respondentes com vistas a revelar as diferentes posturas dos participantes com relação à EAD; o emprego da técnica estatística análise de cluster para agrupar as incertezas e os individuos por similaridades; e uma análise integrada dos resultados advindos das diversas etapas. O nível de consenso foi baixo, resultando em oito incertezas consideradas relevantes para o processo. Destas, 50% são de dimensão metodológica, expressando que durante um processo de inovação a metodologia se destaca por representar mudanças de paradigmas já estabelecidos. O agrupamento de incertezas, por sua vez, revelou oito grandes conjuntos de controvérsias que pressionam de maneiras diferentes o processo de tomada de decisão e operacionalização de sistemas de EAD. Pelas características de cada conjunto, percebe-se que os problemas que perpassam a EAD no Pará fazem parte do contexto atual e contemplam preocupações referentes a pontos que norteiam o processo, a incertezas de caráter geral, ao compromisso político, aos componentes que indicam a qualidade e o reconhecimento da EAD, aos aspectos metodológicos e técnicos, à estabilidade da modalidade, ao acesso e uso das novas tecnologias de informação e comunicação e às condições de infra-estrutura. Durante a concepção de SEADs a orientação cultural influencia o enfoque a ser adotado pelos dirigentes, podendo estar mais direcionado para o controle (hierárquicos), para o respeito ao aluno (igualitários), para a satisfação do aluno (individualistas) e para a visão de desconfiança (fatalistas). A integração de todos os resultados possibilitou indicar critérios de decisão e estratégias para enfrentar as incertezas ou mesmo aprender a conviver com estas. Concluiu-se que o uso da metodologia de AI se mostrou eficaz para o tratamento do problema da EAD no Pará, propiciando uma gestão das incertezas, o que se acredita levar à redução da probabilidade de ocorrência de eventos indesejáveis e/ou inesperados.

Desenvolvimento da ferramenta MS2PSOC: Tradução de modelos descritos no matlab/simulink para o ambiente psoc creator

Pós-graduação em Engenharia Elétrica - FEIS

Diseño, implementación y verificación de un controlador para robots educativos

[EN] This project briefly analyzes the scope and applications of Industrial Robotics, as well as the importance that this technical discipline has gained in the past decades. In addition, it proposes a modern platform to assist in teaching this discipline in colleges and universities. This new educational platform for the teaching of Industrial Robotics is based on the robotic systems from Rhino Robotics Ltd., using the existing robotic arms and replacing the control electronics by a newer, modern and yet backwards-compatible controller. In addition to the controller, this platform also provides new, up-to-date software utilities that are more intuitive than those provided with the old system. The work to be done consists essentially in receiving commands from a personal computer which the controller must interpret in order to control the motors of the robotic arm. The controller itself will be implemented as an embedded system based on microcontrollers. This requires the implementation of a communication protocol between the personal computer and the microcontroller, the design of a command interpreter, the design of the electronics for motor control using PWM and H-bridges, and the implementation of control techniques (more precisely, PID control). Hence, this project combines software and hardware design and integration techniques with motor control techniques and feedback control methods from Control Engineering, along with the kinematic analysis of the Rhino XR-4 robotic arm. 

Aplicación en tiempo real para el control de señales en empotrados

[ES] Este software pretende dar soporte a la monitorización y control de señales provenientes de distintos dispositivos electrónicos a través de un sistema empotrado con un sistema operativo en tiempo real que proporcione las herramientas necesarias para cumplir con los requisitos de tiempo que se plantean. Para ello la aplicación se divide en varios procesos encargados de la lectura y configuración de las distintas señales, control de eventos anómalos (interrupciones, fallos del sistema, etc),  almacenamiento en una base de datos de la información generada y una interfaz de usuario vía web que permita la monitorización del sistema en su conjunto.

Design of wireless sensor networks for fluid dynamic applications

In fluid dynamics research, pressure measurements are of great importance to define the flow field acting on aerodynamic surfaces. In fact the experimental approach is fundamental to avoid the complexity of the mathematical models for predicting the fluid phenomena. It’s important to note that, using in-situ sensor to monitor pressure on large domains with highly unsteady flows, several problems are encountered working with the classical techniques due to the transducer cost, the intrusiveness, the time response and the operating range. An interesting approach for satisfying the previously reported sensor requirements is to implement a sensor network capable of acquiring pressure data on aerodynamic surface using a wireless communication system able to collect the pressure data with the lowest environmental–invasion level possible. In this thesis a wireless sensor network for fluid fields pressure has been designed, built and tested. To develop the system, a capacitive pressure sensor, based on polymeric membrane, and read out circuitry, based on microcontroller, have been designed, built and tested. The wireless communication has been performed using the Zensys Z-WAVE platform, and network and data management have been implemented. Finally, the full embedded system with antenna has been created. As a proof of concept, the monitoring of pressure on the top of the mainsail in a sailboat has been chosen as working example.

Hybrid Methods for Resource Allocation and Scheduling Problems in Deterministic and Stochastic Environments

This work presents exact, hybrid algorithms for mixed resource Allocation and Scheduling problems; in general terms, those consist into assigning over time finite capacity resources to a set of precedence connected activities. The proposed methods have broad applicability, but are mainly motivated by applications in the field of Embedded System Design. In particular, high-performance embedded computing recently witnessed the shift from single CPU platforms with application-specific accelerators to programmable Multi Processor Systems-on-Chip (MPSoCs). Those allow higher flexibility, real time performance and low energy consumption, but the programmer must be able to effectively exploit the platform parallelism. This raises interest in the development of algorithmic techniques to be embedded in CAD tools; in particular, given a specific application and platform, the objective if to perform optimal allocation of hardware resources and to compute an execution schedule. On this regard, since embedded systems tend to run the same set of applications for their entire lifetime, off-line, exact optimization approaches are particularly appealing. Quite surprisingly, the use of exact algorithms has not been well investigated so far; this is in part motivated by the complexity of integrated allocation and scheduling, setting tough challenges for ``pure'' combinatorial methods. The use of hybrid CP/OR approaches presents the opportunity to exploit mutual advantages of different methods, while compensating for their weaknesses. In this work, we consider in first instance an Allocation and Scheduling problem over the Cell BE processor by Sony, IBM and Toshiba; we propose three different solution methods, leveraging decomposition, cut generation and heuristic guided search. Next, we face Allocation and Scheduling of so-called Conditional Task Graphs, explicitly accounting for branches with outcome not known at design time; we extend the CP scheduling framework to effectively deal with the introduced stochastic elements. Finally, we address Allocation and Scheduling with uncertain, bounded execution times, via conflict based tree search; we introduce a simple and flexible time model to take into account duration variability and provide an efficient conflict detection method. The proposed approaches achieve good results on practical size problem, thus demonstrating the use of exact approaches for system design is feasible. Furthermore, the developed techniques bring significant contributions to combinatorial optimization methods.

Constraint based methods for allocation and scheduling of periodic applications

This work presents exact algorithms for the Resource Allocation and Cyclic Scheduling Problems (RA&CSPs). Cyclic Scheduling Problems arise in a number of application areas, such as in hoist scheduling, mass production, compiler design (implementing scheduling loops on parallel architectures), software pipelining, and in embedded system design. The RA&CS problem concerns time and resource assignment to a set of activities, to be indefinitely repeated, subject to precedence and resource capacity constraints. In this work we present two constraint programming frameworks facing two different types of cyclic problems. In first instance, we consider the disjunctive RA&CSP, where the allocation problem considers unary resources. Instances are described through the Synchronous Data-flow (SDF) Model of Computation. The key problem of finding a maximum-throughput allocation and scheduling of Synchronous Data-Flow graphs onto a multi-core architecture is NP-hard and has been traditionally solved by means of heuristic (incomplete) algorithms. We propose an exact (complete) algorithm for the computation of a maximum-throughput mapping of applications specified as SDFG onto multi-core architectures. Results show that the approach can handle realistic instances in terms of size and complexity. Next, we tackle the Cyclic Resource-Constrained Scheduling Problem (i.e. CRCSP). We propose a Constraint Programming approach based on modular arithmetic: in particular, we introduce a modular precedence constraint and a global cumulative constraint along with their filtering algorithms. Many traditional approaches to cyclic scheduling operate by fixing the period value and then solving a linear problem in a generate-and-test fashion. Conversely, our technique is based on a non-linear model and tackles the problem as a whole: the period value is inferred from the scheduling decisions. The proposed approaches have been tested on a number of non-trivial synthetic instances and on a set of realistic industrial instances achieving good results on practical size problem.

Sparse Signal Representation of Ultrasonic Signals for Structural Health Monitoring Applications

Assessment of the integrity of structural components is of great importance for aerospace systems, land and marine transportation, civil infrastructures and other biological and mechanical applications. Guided waves (GWs) based inspections are an attractive mean for structural health monitoring. In this thesis, the study and development of techniques for GW ultrasound signal analysis and compression in the context of non-destructive testing of structures will be presented. In guided wave inspections, it is necessary to address the problem of the dispersion compensation. A signal processing approach based on frequency warping was adopted. Such operator maps the frequencies axis through a function derived by the group velocity of the test material and it is used to remove the dependence on the travelled distance from the acquired signals. Such processing strategy was fruitfully applied for impact location and damage localization tasks in composite and aluminum panels. It has been shown that, basing on this processing tool, low power embedded system for GW structural monitoring can be implemented. Finally, a new procedure based on Compressive Sensing has been developed and applied for data reduction. Such procedure has also a beneficial effect in enhancing the accuracy of structural defects localization. This algorithm uses the convolutive model of the propagation of ultrasonic guided waves which takes advantage of a sparse signal representation in the warped frequency domain. The recovery from the compressed samples is based on an alternating minimization procedure which achieves both an accurate reconstruction of the ultrasonic signal and a precise estimation of waves time of flight. Such information is used to feed hyperbolic or elliptic localization procedures, for accurate impact or damage localization.

Classificazione di oggetti in immagini attraverso il modello Bag of Visual Words

Generic object recognition is an important function of the human visual system and everybody finds it highly useful in their everyday life. For an artificial vision system it is a really hard, complex and challenging task because instances of the same object category can generate very different images, depending of different variables such as illumination conditions, the pose of an object, the viewpoint of the camera, partial occlusions, and unrelated background clutter. The purpose of this thesis is to develop a system that is able to classify objects in 2D images based on the context, and identify to which category the object belongs to. Given an image, the system can classify it and decide the correct categorie of the object. Furthermore the objective of this thesis is also to test the performance and the precision of different supervised Machine Learning algorithms in this specific task of object image categorization. Through different experiments the implemented application reveals good categorization performances despite the difficulty of the problem. However this project is open to future improvement; it is possible to implement new algorithms that has not been invented yet or using other techniques to extract features to make the system more reliable. This application can be installed inside an embedded system and after trained (performed outside the system), so it can become able to classify objects in a real-time. The information given from a 3D stereocamera, developed inside the department of Computer Engineering of the University of Bologna, can be used to improve the accuracy of the classification task. The idea is to segment a single object in a scene using the depth given from a stereocamera and in this way make the classification more accurate.

Generatore di entropia basato su dinamica caotica con interfaccia usb

È impossibile implementare sorgenti autenticamente casuali su hardware digitale. Quindi, storicamente, si è fatto ampio uso di generatori di numeri pseudo-casuali, evitando così i costi necessari per la progettazione di hardware analogico dedicato. Tuttavia, le sorgenti pseudo-casuali hanno proprietà (riproducibilità e periodicità) che si trasformano in vulnerabilità, nel caso in cui vengano adottate in sistemi di sicurezza informatica e all’interno di algoritmi crittografici. Oggi la richiesta di generatori di numeri autenticamente casuali è ai suoi massimi storici. Alcuni importanti attori dell’ICT sviluppato proprie soluzioni dedicate, ma queste sono disponibili solo sui sistemi moderni e di fascia elevata. È quindi di grande attualità rendere fruibili generatori autenticamente casuali per sistemi già esistenti o a basso costo. Per garantire sicurezza e al tempo stesso contenere i costi di progetto è opportuno pensare ad architetture che consentano di riusare parti analogiche già disponibili. Particolarmente interessanti risultano alcune architetture che, grazie all’utilizzo di dinamiche caotiche, consentono di basare buona parte della catena analogica di elaborazione su ADC. Infatti, tali blocchi sono ampiamente fruibili in forma integrata su architetture programmabili e microcontrollori. In questo lavoro, si propone un’implementazione a basso costo ed elevata flessibilità di un architettura basata su un ADC, inizialmente concepita all’Università di Bologna. La riduzione di costo viene ottenuta sfruttando il convertitore già presente all’interno di un microcontrollore. L’elevata flessibilità deriva dal fatto che il microcontrollore prescelto mette a disposizione una varietà di interfacce di comunicazione, tra cui quella USB, con la quale è possibile rendere facilmente fruibili i numeri casuali generati. Quindi, l’intero apparato comprende solo un microcontrollore e una minima catena analogica di elaborazione esterna e può essere interfacciato con estrema facilità ad elaboratori elettronici o sistemi embedded. La qualità della proposta, in termini di statistica delle sequenze casuali generate, è stata validata sfruttando i test standardizzati dall’U.S. NIST.

Progettazione ed implementazione di un dispositivo portabile per l'acquisizione ed il filtraggio di segnali biomedici

The use of wearable devices for the monitoring of biological potentials is an ever-growing area of research. Wearable devices for the monitoring of vital signs such as heart-rate, respiratory rate, cardiac output and blood oxygenation are necessary in determining the overall health of a patient and allowing earlier detection of adverse events such as heart attacks and strokes and earlier diagnosis of disease. This thesis describes a bio-potential acquisition embedded system designed with an innovative analog front-end, showing the performance in EMG and ECG applications and the comparison between different noise reduction algorithms. We demonstrate that the proposed system is able to acquire bio-potentials with a signal quality equivalent to state of the art bench-top biomedical devices and can be therefore used for monitoring purpose, with the advantages of a low-cost low-power wearable device.

"Pillowe": progettazione e sviluppo di un cuscino intelligente

Progettazione di un cuscino che si occupa di noi e ci aiuta nell'addormentarci attraverso la musica. Il tutto grazie all'aiuto di sensori e dell'Arduino che comunicheranno con lo smartphone per dare un'esperienza flessibile e personalizzabile.

Integración MPlayer-OpenSVC en el procesador multinúcleo OMAP3530

La constante evolución de dispositivos portátiles multimedia que se ha producido en la última década ha provocado que hoy en día se disponga de una amplia variedad de dispositivos con capacidad para reproducir contenidos multimedia. En consecuencia, la reproducción de esos contenidos en dichos terminales lleva asociada disponer de procesadores que soporten una alta carga computacional, ya que las tareas de descodificación y presentación de video así lo requieren. Sin embargo, un procesador potente trabajando a elevadas frecuencias provoca un elevado consumo de la batería, y dado que se pretende trabajar con dispositivos portátiles, la vida útil de la batería se convierte en un asunto de especial importancia. La problemática que se plantea se ha convertido en una de las principales líneas de investigación del Grupo de Investigación GDEM (Grupo de Diseño Electrónico y Microelectrónico). En esta línea de trabajo, se persigue cómo optimizar el consumo de energía en terminales portables desde el punto de vista de la reducción de la calidad de experiencia del usuario a cambio de una mayor autonomía del terminal. Por tanto, para lograr esa reducción de la calidad de experiencia mencionada, se requiere un estándar de codificación de vídeo que así lo permita. El Grupo de Investigación GDEM cuenta con experiencia en el estándar de vídeo escalable H.264/SVC, el cual permite degradar la calidad de experiencia en función de las necesidades/características del dispositivo. Más concretamente, un video escalable contiene embebidas distintas versiones del video original que pueden ser descodificadas en diferentes resoluciones, tasas de cuadro y calidades (escalabilidades espacial, temporal y de calidad respectivamente), permitiendo una adaptación rápida y muy flexible. Seleccionado el estándar H.264/SVC para las tareas de vídeo, se propone trabajar con Mplayer, un reproductor de vídeos de código abierto (open source), al cual se le ha integrado un descodificador para vídeo escalable denominado OpenSVC. Por último, como dispositivo portable se trabajará con la plataforma de desarrollo BeagleBoard, un sistema embebido basado en el procesador OMAP3530 que permite modificar la frecuencia de reloj y la tensión de alimentación dinámicamente reduciendo de este modo el consumo del terminal. Este procesador a su vez contiene integrados un procesador de propósito general (ARM Cortex-A8) y un procesador digital de señal (DSP TMS320C64+TM). Debido a la alta carga computacional de la descodificación de vídeos escalables y la escasa optimización del ARM para procesamiento de datos, se propone llevar a cabo la ejecución de Mplayer en el ARM y encargar la tarea de descodificación al DSP, con la finalidad de reducir el consumo y por tanto aumentar la vida útil del sistema embebido sobre el cual se ejecutará la aplicación desarrollada. Una vez realizada esa integración, se llevará a cabo una caracterización del descodificador alojado en el DSP a través de una serie de medidas de rendimiento y se compararán los resultados con los obtenidos en el proceso de descodificación realizado únicamente en el ARM. ABSTRACT During the last years, the multimedia portable terminals have gradually evolved causing that nowadays a several range of devices with the ability of playing multimedia contents are easily available for everyone. Consequently, those multimedia terminals must have high-performance processors to play those contents because the coding and decoding tasks demand high computational load. However, a powerful processor performing to high frequencies implies higher battery consumption, and this issue has become one of the most important problems in the development cycle of a portable terminal. The power/energy consumption optimization on multimedia terminals has become in one the most significant work lines in the Electronic and Microelectronic Research Group of the Universidad Politécnica de Madrid. In particular, the group is researching how to reduce the user‟s Quality of Experience (QoE) quality in exchange for increased battery life. In order to reduce the Quality of Experience (QoE), a standard video coding that allows this operation is required. The H.264/SVC allows reducing the QoE according to the needs/characteristics of the terminal. Specifically, a scalable video contains different versions of original video embedded in an only one video stream, and each one of them can be decoded in different resolutions, frame rates and qualities (spatial, temporal and quality scalabilities respectively). Once the standard video coding is selected, a multimedia player with support for scalable video is needed. Mplayer has been proposed as a multimedia player, whose characteristics (open-source, enormous flexibility and scalable video decoder called OpenSVC) are the most suitable for the aims of this Master Thesis. Lastly, the embedded system BeagleBoard, based on the multi-core processor OMAP3530, will be the development platform used in this project. The multimedia terminal architecture is based on a commercial chip having a General Purpose Processor (GPP – ARM Cortex A8) and a Digital Signal Processor (DSP, TMS320C64+™). Moreover, the processor OMAP3530 has the ability to modify the operating frequency and the supply voltage in a dynamic way in order to reduce the power consumption of the embedded system. So, the main goal of this Master Thesis is the integration of the multimedia player, MPlayer, executed at the GPP, and scalable video decoder, OpenSVC, executed at the DSP in order to distribute the computational load associated with the scalable video decoding task and to reduce the power consumption of the terminal. Once the integration is accomplished, the performance of the OpenSVC decoder executed at the DSP will be measured using different combinations of scalability values. The obtained results will be compared with the scalable video decoding performed at the GPP in order to show the low optimization of this kind of architecture for decoding tasks in contrast to DSP architecture.