Superconductivity in metal-mixed ion-implanted polymer films

Ion implantation of normally insulating polymers offers an alternative to depositing conjugated organics onto plastic films to make electronic circuits. We used a 50 keV nitrogen ion beam to mix a thin 10 nm Sn/Sb alloy film into the subsurface of polyetheretherketone and report the low temperature properties of this material. We observed metallic behavior, and the onset of superconductivity below 3 K. There are strong indications that the superconductivity does not result from a residual thin film of alloy, but instead from a network of alloy grains coupled via a weakly conducting, ion-beam carbonized polymer matrix. (c) 2006 American Institute of Physics.

The mammalian MAPK/ERK pathway exhibits properties of a negative feedback amplifier

Three-tiered kinase modules, such as the Raf-MEK (mitogen-activated or extracellular signal-regulated protein kinase kinase)-ERK (extracellular signal-regulated kinase) mitogen-activated protein kinase pathway, are widespread in biology, suggesting that this structure conveys evolutionarily advantageous properties. We show that the three-tiered kinase amplifier module combined with negative feedback recapitulates the design principles of a negative feedback amplifier (NFA), which is used in electronic circuits to confer robustness, output stabilization, and linearization of nonlinear signal amplification. We used mathematical modeling and experimental validation to demonstrate that the ERK pathway has properties of an NFA that (i) converts intrinsic switch-like activation kinetics into graded linear responses, (ii) conveys robustness to changes in rates of reactions within the NFA module, and (iii) stabilizes outputs in response to drug-induced perturbations of the amplifier. These properties determine biological behavior, including activation kinetics and the response to drugs.

Software and hardware aspects of a microprocessor controlled lathe

A small lathe has been modified to work under microprocessor control to enhance the facilities which the lathe offers and provide a wider operating range with relevant economic gains. The result of these modifications give better operating system characteristics. A system of electronic circuits have been developed, utilising the latest technology, to replace the pegboard with the associated obsolete electrical components. Software for the system includes control programmes for the implementation of the original pegboard operation and several sample machine code programmes are included, covering a wide spectrum of applications, including diagnostic testing of the control system. It is concluded that it is possible to carry out a low cost retrofit on existing machine tools to enhance their range of capabilities.

Racioethnic Diversity on the Web: A Lost Opportunity

The authors report the generally poor results attained when the NAACP assessed the diversity management performance of 16 major hotel companies. Then, as an alternative means of assessing the same hotel companies’ commitment to diversity, they report the results of an analysis of the world-wide web pages the companies use to represent themselves in the electronic marketplace. Analysis of the web sites found virtually no evidence of corporate concern for diversity.

Applications of a Collaborative Open Object Oriented Learning Environment to Electronics, Computing and Mathematics Education

A lightweight Java application suite has been developed and deployed allowing collaborative learning between students and tutors at remote locations. Students can engage in group activities online and also collaborate with tutors. A generic Java framework has been developed and applied to electronics, computing and mathematics education. The applications are respectively: (a) a digital circuit simulator, which allows students to collaborate in building simple or complex electronic circuits; (b) a Java programming environment where the paradigm is behavioural-based robotics, and (c) a differential equation solver useful in modelling of any complex and nonlinear dynamic system. Each student sees a common shared window on which may be added text or graphical objects and which can then be shared online. A built-in chat room supports collaborative dialogue. Students can work either in collaborative groups or else in teams as directed by the tutor. This paper summarises the technical architecture of the system as well as the pedagogical implications of the suite. A report of student evaluation is also presented distilled from use over a period of twelve months. We intend this suite to facilitate learning between groups at one or many institutions and to facilitate international collaboration. We also intend to use the suite as a tool to research the establishment and behaviour of collaborative learning groups. We shall make our software freely available to interested researchers.

Carbon nanotube films for flexible electronics

Discovering scalable routes to fabricate large scale electronic devices on flexible substrates has been the goal of the newly emerging field of flexible macroelectronics. Thin film transistors (TFTs) have been fabricated on flexible substrates by using organic small-molecule and polymer-based materials, or thin layers of crystalline inorganic semiconductors. Recently, films of carbon nanotubes have been proposed as electronic materials with superior electrical performance due to exceptional electrical and mechanical properties of single-walled carbon nanotubes (SWCNTs). In this thesis, some aspects of recent research efforts on integrating arrays of carbon nanotubes into macroelectronic devices are described. Carbon nanotube films have two major uses for flexible macroelectronics. The first approach uses carbon nanotube thin films as active semiconducting materials in the channel of flexible TFTs. Even though, high-performance carbon nanotube thin film transistors have been realized, the electronic non-homogeneity of the as-grown carbon nanotubes in the film limits the device performance for some applications. In this thesis, the application of electrochemical functionalization on carbon nanotube films to improve the electronic homogeneity of the film is described. The effect of the crystal quartz substrates on the growth rate of carbon nanotubes, and whether this can be used to sort out as-grown carbon nanotubes by electronic type is also discussed. Finally, I argue that high density carbon nanotube films can also be used as highly conducting stretchable interconnects on mechanically flexible electronic circuits. The sheet resistance and the nature of the buckling of carbon nanotube films on flexible substrates are discussed.

Caracterización analítica y antioxidante de uvas Pedro Ximénez y Tempranillo durante su pasificación. Potencial enológico de la variedad Tempranillo pasificada

En esta Tesis Doctoral se estudian la pasificación de las uvas Pedro Ximénez y Tempranillo, y la obtención de vinos dulces de uvas Tempranillo pasificadas. Durante la pasificación aumentan los azúcares, el pH, la acidez titulable y la acidez volátil. Los compuestos con aroma herbáceo disminuyen y los de aroma a fruta madura aumentan. En Tempranillo también aumentan los aromas especiados y a hierba seca. La nariz electrónica se revela como herramienta de análisis rápida y sencilla para decidir el punto óptimo de pasificación en función de la composición volátil. Parece existir un óptimo de pasificación sobre el 25% de deshidratación. La composición fenólica y la actividad antioxidante de mostos aumentan con la pasificación, mientras que disminuyen en los hollejos. Los valores de ambas variables son superiores en Tempranillo. En Pedro Ximénez la fracción más influyente varía durante la pasificación, siendo al final de la misma la correspondiente a las procianidinas poliméricas. En Tempranillo son los antocianos los que más contribuyen a la actividad antioxidante. Los ensayos in vitro con Pedro Ximénez demuestran que tanto los mostos como sus extractos fenólicos protegen al ADN, a lípidos, azúcares y proteínas de la oxidación provocada por distintos radicales libres. Los ensayos in vivo manifiestan que la incubación de las levadura con los mostos de uvas Pedro Ximénez y Tempranillo pasificadas, les confiere un claro efecto protector frente al estrés oxidativo. Efecto que aumenta con el grado de pasificación. Los hollejos de la variedad Tempranillo se han mostrado más efectivos que los mostos en esta protección. El contenido en compuestos volátiles es mayor en los vinos dulces de uvas Tempranillo pasificadas obtenidos por fermentación parcial que en los elaborados por el método tradicional, siendo también los mejor valorados organolépticamente.

Development of a technique for the formation of discrete microconnection; internal research.

Mode of access: Internet.

Design and characterization of wideband Hall current sensors in BCD technology for smart power and metering applications

Power electronic circuits are moving towards higher switching frequencies, exploiting the capabilities of novel devices to shrink the dimension of passive components. This trend demands sensors capable enough to operate at such high frequencies. This thesis aims to demonstrate through experimental characterization, the broadband capability of a fully integrated CMOS X-Hall current sensor in current mode interfaced with a transimpedance amplifier (TIA), chip CH09, realized in CMOS technology for power electronics applications such as power converters. The system exploits a common-mode control system to operate the dual supply system, 5-V for the X-Hall probe and 1.2-V for the readout. The developed prototype achieves a maximum acquisition bandwidth of 12 MHz, a power consumption of 11.46 mW, resolution of 39 mArms, a sensitivity of 8 % /T, and a FoM of 569-MHz/A2mW, significantly higher than current state-of-the-art. Further enhancements were proposed to CH09 as a new chip CH100, aiming for accuracy levels prerequisite for a real-time power electronic application. The TIA was optimized for a wider bandwidth of 26.7 MHz with nearly 30% reduction of the integrated input referred noise of 26.69 nArms at the probe-AFE interface in the frequency band of DC-30 MHz, and a 10% improvement in the dynamic range. The expected input range is 5-A. The chip incorporates a dual sensing chain for differential sensing to overcome common mode interferences. A novel offset cancellation technique is proposed that would require switching of polarity of bias currents. Thermal gain drift was improved by a factor of 8 and will be digitally calibrated utilizing a new built-in temperature sensor with a post calibration measurement accuracy greater than 1%. The estimated power consumption of the entire system is 55.6 mW. Both prototypes have been implemented through a 90-nm microelectronic process from STMicroelectronics and occupy a silicon area of 2.4 mm2.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Feasibility of Electronic Tap-Changing Stabilizers for Medium Voltage Lines-Precedents and New Configurations

Thyristor-based onload tap-changing ac voltage stabilizers are cheap and robust. They have replaced most mechanical tap-changers in low voltage applications from 300 VA to 300 M. Nevertheless, this replacement hardily applies to tap-changers associated to transformers feeding medium-voltage lines (typically 69 kV primary, 34.5 kV line, 10 MVA) which need periodical maintenance of contacts and oil. The Electric Power Research Institute (EPRI) has studied the feasibility of this replacement. It detected economical problems derived from the need for series association of thyristors to manage the high voltages involved, and from the current overload developed under line fault. The paper reviews the configurations used in that field and proposes new solutions, using a compensating transformer in the main circuit and multi-winding coils in the commutating circuit, with reduced overload effect and no series association of thyristors, drastically decreasing their number and rating. The stabilizer can be installed at any point of the line and the electronic circuit can be fixed to ground. Subsequent works study and synthesize several commutating circuits in detail.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

Data analysis in multiple-frequency bioelectrical impedance analysis

The performance of three analytical methods for multiple-frequency bioelectrical impedance analysis (MFBIA) data was assessed. The methods were the established method of Cole and Cole, the newly proposed method of Siconolfi and co-workers and a modification of this procedure. Method performance was assessed from the adequacy of the curve fitting techniques, as judged by the correlation coefficient and standard error of the estimate, and the accuracy of the different methods in determining the theoretical values of impedance parameters describing a set of model electrical circuits. The experimental data were well fitted by all curve-fitting procedures (r = 0.9 with SEE 0.3 to 3.5% or better for most circuit-procedure combinations). Cole-Cole modelling provided the most accurate estimates of circuit impedance values, generally within 1-2% of the theoretical values, followed by the Siconolfi procedure using a sixth-order polynomial regression (1-6% variation). None of the methods, however, accurately estimated circuit parameters when the measured impedances were low (<20 Omega) reflecting the electronic limits of the impedance meter used. These data suggest that Cole-Cole modelling remains the preferred method for the analysis of MFBIA data.

Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C-gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET's has been reviewed and demonstrated. By analyzing the change in C-gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I-bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q(ot), through gate-to-substrate capacitance (C-gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device's structure. (C) 2001 Elsevier Science Ltd. All rights reserved.

Analysis of an array of monopoles with the use of a radial waveguide approach

A radial guide field matching method (RGFMM) is used to analyze a circular array antenna consisting of one active monopole surrounded by a concentric array of passive monopoles terminated in arbarary loads. An equivalent admittance matrix for this antenna system is determined to study the input admittance of the active monopole when the peripheral elements are terminated in open or short circuits. RGFMM results are compared with free-space method of moments (FS-MoM) results for a small switched-beam array a seven monopoles. Good agreement is noted. (C) 2002 Wiley Periodicals, Inc.