971 resultados para Design procedure


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A simple and general design procedure is presented for the polarisation diversity of arbitrary conformal arrays; this procedure is based on the mathematical framework of geometric algebra and can be solved optimally using convex optimisation. Aside from being simpler and more direct than other derivations in the literature, this derivation is also entirely general in that it expresses the transformations in terms of rotors in geometric algebra which can easily be formulated for any arbitrary conformal array geometry. Convex optimisation has a number of advantages; solvers are widespread and freely available, the process generally requires a small number of iterations and a wide variety of constraints can be readily incorporated. The study outlines a two-step approach for addressing polarisation diversity in arbitrary conformal arrays: first, the authors obtain the array polarisation patterns using geometric algebra and secondly use a convex optimisation approach to find the optimal weights for the polarisation diversity problem. The versatility of this approach is illustrated via simulations of a 7×10 cylindrical conformal array. © 2012 The Institution of Engineering and Technology.

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This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

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In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

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The work presented is concerned with the estimation of manufacturing cost at the concept design stage, when little technical information is readily available. The work focuses on the nose cowl sections of a wide range of engine nacelles built at Bombardier Aerospace Shorts of Belfast. A core methodology is presented that: defines manufacturing cost elements that are prominent; utilises technical parameters that are highly influential in generating those costs; establishes the linkage between these two; and builds the associated cost estimating relations into models. The methodology is readily adapted to deal with both the early and more mature conceptual design phases, which thereby highlights the generic, flexible and fundamental nature of the method. The early concept cost model simplifies cost as a cumulative element that can be estimated using higher level complexity ratings, while the mature concept cost model breaks manufacturing cost down into a number of constituents that are each driven by their own specific drivers. Both methodologies have an average error of less that ten percent when correlated with actual findings, thus achieving an acceptable level of accuracy. By way of validity and application, the research is firmly based on industrial case studies and practice and addresses the integration of design and manufacture through cost. The main contribution of the paper is the cost modelling methodology. The elemental modelling of the cost breakdown structure through materials, part fabrication, assembly and their associated drivers is relevant to the analytical design procedure, as it utilises design definition and complexity that is understood by engineers.

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The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

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The impact that the transmission-line load-network has on the performance of the recently introduced series-L/parallel-tuned Class-E amplifier and the classic shunt-C/series-tuned configuration when compared to optimally derived lumped load networks is discussed. In addition an improved load topology which facilitates harmonic suppression of up to 5 order as required for maximum Class-E efficiency as well as load resistance transformation and a design procedure involving the use of Kuroda's identity and Richard's transformation enable a distributed synthesis process which dispenses with the need for iterative tuning as previously required in order to achieve optimum Class-E operation. © 2005 IEEE.

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An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

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Anisotropic impedance surfaces are employed as low-profile and broadband reflectors that convert orthogonal linear to right- and left-handed circular polarization respectively. By virtue of anisotropy, it is possible to independently control the reflection characteristics of two orthogonal linearly polarized incident plane waves and therefore achieve linear to circular polarization conversion. Equivalent circuits for anisotropic impedance surfaces with arbitrarily shaped elements are employed to demonstrate the operating principle and a design procedure is proposed. The proposed design procedure is demonstrated by means of an example involving a dipole array. A prototype is designed and its performance characteristics are evaluated. The 3-dB relative axial ratio bandwidth exceeds 60%, while low loss and angular stability are also reported. Numerical and experimental results on a fabricated prototype are presented to validate the synthesis and the performance. © 2006 IEEE.

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A Digital Video Broadcast Terrestrial (DVB-T) based passive radar requires the development of an antenna array that performs satisfactorily over the entire DVB-T band. The array should require no mechanical adjustments to inter-element spacing to correspond to the DVB-T carrier frequency used for any particular measurement. This paper will describe the challenges involved in designing an antenna array with a bandwidth of 450 MHz. It will discuss the design procedure and demonstrate a number of simulated array configurations. The final configuration of the array will be shown as well as simulations of the expected performance over the desired frequency span.

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Two Liquid crystal-based reflectarrays that operate at 100 GHz and 125 GHz are presented. The first prototype (100 GHz) is used to validate the modeling and the design procedure proposed for this class of antenna. Experimental validation of the beam scanning is carried out by measuring the received power in a quasi-optical test bench, which is able to rotate the receiver in the horizontal plane. These results are used to design a second prototype antenna (125 GHz) which exhibits 2D beam scanning capabilities with a large bandwidth and scanning range that is sufficient for radar and communications applications.

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A compact highly linear microstrip dual-mode electronically switchable filter is presented. The key characteristics of the dual-mode switchable filter are investigated and described. A second order filter design procedure is outlined to facilitate the realisation of Butterworth and Chebyshev functions. The proposed filter was built and tested with NXP pin diode model BAP65-03. The measured and simulated results are in good agreement. The measured insertion loss in the ON state was 3.0 dB the isolation in the OFF state was 45 dB at the centre frequency. An evaluation of filter distortion is presented for digitally modulated 16 QAM and QPSK signals.

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A compact highly linear microstrip dual - mode optically switchable filter and a reconfigurable power amplifier are presented. The key characteristics of the dual - mode switchable filter are investigated and described. A second order filter design procedure is outlined to facilitate the realisation of Butterworth and Chebyshev functions. The proposed filter was built and tested with an optical switch, which comprised of a silicon dice acti vated using near infrared light. The measured and simulated results are in good agreement. The measured insertion loss in the ON state was 3.0 dB the isolation in the OFF state was 45 dB at the centre frequency. An evaluation of filter distortion is presen ted for digitally modulated M - QAM and M - QAM OFDM singals.

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This paper presents an optically reconfigurable E-plane waveguide resonator and filter. N-type silicon dice doped with phosphorus is used as the switching element and is connected to the edge of a metallic fin. Illumination of the silicon dice allows realization of a different length of the fin, thus creating a shift in resonant frequency of the structure. Frequency tuning range up to about 5.2% is achieved for the resonator as well as the filter. Measurements on a fabricated optically reconfigurable resonator confirm the accuracy of the design procedure. Measured responses show good agreement with simulation.

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A novel compact tunable bandstop filter using Defected Microstrip Structure (DMS) is presented in this paper. The structure utilizes a modified T shaped DMS which helps in miniaturization of the filter. To verify the concept, one such filter was simulated, designed, fabricated and tested. Measurements on a fabricated tunable filter confirm the accuracy of the design procedure. The tuning range of 20% is achieved, ranging from 2.26 GHz to 2.747 GHz. Tuning is achieved by using NXP BB179 varactor diode. A nonlinear distortion evaluation in a tunable filter was experimentally verified. Experimental verification shows the filter is highly linear.

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A novel, compact and highly selective microstrip bandpass filter with bandwidth reconfigurability for ultra-wideband (UWB) applications is presented. The proposed design uses stepped impedance resonator (SIR) for realization of bandpass filter (BPF) and employs a single varactor diode (BB135-NXP) for the purpose of reconfiguring bandwidth. Additionally, to improve the selectivity between passband edges, a cross-coupling between I/O feed lines is introduced which generated pairs of attenuation poles at each side of the passband. Measurements on a fabricated reconfigurable filter confirm the accuracy of the design procedure. Measured responses show good agreement with simulation. The proposed filter is able to achieve significant size reduction (8.5 mm × 7.1 mm excluding the feeding ports) as compared to the conventional bandpass filters with reconfigurable bandwidth.