Effect of rosemary (Rosmarinus officinalis) extract on weight, hematology and cell-mediated immune response of newborn goat kids

This study aimed at evaluating the effects of different levels of rosemary (Rosmarinus officinalis) extract on growth rate, hematology and cell-mediated immune response in Markhoz newborn goat kids. Twenty four goat kids (aged 7 +/- 3 days) were randomly allotted to four groups with six replicates. The groups included: control, T1, T2 and T3 groups which received supplemented-milk with 0, 100, 200 and 400mg aqueous rosemary extract per kg of live body weight per day for 42 days. Body weights of kids were measured weekly until the end of the experiment. On day 42, 10 ml blood samples were collected from each kid through the jugular vein. Cell-mediated immune response was assessed through the double skin thickness after intradermal injection of phyto-hematoglutinin (PHA) at day 21 and 42. No significant differences were seen in initial body weight, average daily gain (ADG) and total gain. However, significant differences in globulin (P <0.05), and white blood cells (WBC) (P <0.001) were observed. There were no significant differences in haemoglobin (Hb), packed cell volume (PCV), red blood cells (RBC), lymphocytes and neutrophils between the treatments. Skin thickness in response to intra dermal injection of PHA significantly increased in the treated groups as compared to the control group at day 42 (P< 0.01) with the T3 group showing the highest response to PHA injection. In conclusion, the results indicated that aqueous rosemary extract supplemented-milk had a positive effect on immunity and skin thickness of newborn goat kids.

Effect of within-litter birth weight variation on piglet survival and pre-weaning weight gain in a commercial herd

There are several factors that affect piglet survival and this has a bearing on sow productivity. Ten variables that influence pre-weaning vitality were analysed using records from the Pig Industry Board, Zimbabwe. These included individual piglet birth weight, piglet origin (nursed in original litter or fostered), sex, relative birth weight expressed as standard deviation units, sow parity, total number of piglets born, year and month of farrowing, within-litter variability and the presence of stillborn or mummified littermates. The main factors that influenced piglet mortality were fostering, parity and within-litter variability especially the weight of the individual piglet relative to the average of the litter (P<0.05). Presence of a mummified or stillborn littermate, which could be a proxy for unfavourable uterine environment or trauma during the birth process, did not influence pre-weaning mortality. Variability within a litter and the deviation of the weight of an individual piglet from the litter mean, influenced survival to weaning. It is, therefore, advisable for breeders to include uniformity within the litter as a selection criterion. The recording of various variables by farmers seems to be a useful management practice to identify piglets at risk so as to establish palliative measures. Further, farmers should know which litters and which piglets within a litter are at risk and require more attention.

Noise Reduction Using Low Weight and Constant Weight Coding Techniques

Signalling off-chip requires significant current. As a result, a chip's power-supply current changes drastically during certain output-bus transitions. These current fluctuations cause a voltage drop between the chip and circuit board due to the parasitic inductance of the power-supply package leads. Digital designers often go to great lengths to reduce this "transmitted" noise. Cray, for instance, carefully balances output signals using a technique called differential signalling to guarantee a chip has constant output current. Transmitted-noise reduction costs Cray a factor of two in output pins and wires. Coding achieves similar results at smaller costs.

Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

New Architectural Models for Visibly Controllable Computing: The Relevance of Dynamic Object Oriented Architectures and Plan Based Computing Models

Traditionally, we've focussed on the question of how to make a system easy to code the first time, or perhaps on how to ease the system's continued evolution. But if we look at life cycle costs, then we must conclude that the important question is how to make a system easy to operate. To do this we need to make it easy for the operators to see what's going on and to then manipulate the system so that it does what it is supposed to. This is a radically different criterion for success. What makes a computer system visible and controllable? This is a difficult question, but it's clear that today's modern operating systems with nearly 50 million source lines of code are neither. Strikingly, the MIT Lisp Machine and its commercial successors provided almost the same functionality as today's mainstream sytsems, but with only 1 Million lines of code. This paper is a retrospective examination of the features of the Lisp Machine hardware and software system. Our key claim is that by building the Object Abstraction into the lowest tiers of the system, great synergy and clarity were obtained. It is our hope that this is a lesson that can impact tomorrow's designs. We also speculate on how the spirit of the Lisp Machine could be extended to include a comprehensive access control model and how new layers of abstraction could further enrich this model.

A Privacy Conscious Bluetooth Infrastructure for Location Aware Computing

We present a low cost and easily deployed infrastructure for location aware computing that is built using standard Bluetooth® technologies and personal computers. Mobile devices are able to determine their location to room-level granularity with existing bluetooth technology, and to even greater resolution with the use of the recently adopted bluetooth 1.2 specification, all while maintaining complete anonymity. Various techniques for improving the speed and resolution of the system are described, along with their tradeoffs in privacy. The system is trivial to implement on a large scale – our network covering 5,000 square meters was deployed by a single student over the course of a few days at a cost of less than US$1,000.

Failure-Oblivious Computing and Boundless Memory Blocks

Memory errors are a common cause of incorrect software execution and security vulnerabilities. We have developed two new techniques that help software continue to execute successfully through memory errors: failure-oblivious computing and boundless memory blocks. The foundation of both techniques is a compiler that generates code that checks accesses via pointers to detect out of bounds accesses. Instead of terminating or throwing an exception, the generated code takes another action that keeps the program executing without memory corruption. Failure-oblivious code simply discards invalid writes and manufactures values to return for invalid reads, enabling the program to continue its normal execution path. Code that implements boundless memory blocks stores invalid writes away in a hash table to return as the values for corresponding out of bounds reads. he net effect is to (conceptually) give each allocated memory block unbounded size and to eliminate out of bounds accesses as a programming error. We have implemented both techniques and acquired several widely used open source servers (Apache, Sendmail, Pine, Mutt, and Midnight Commander).With standard compilers, all of these servers are vulnerable to buffer overflow attacks as documented at security tracking web sites. Both failure-oblivious computing and boundless memory blocks eliminate these security vulnerabilities (as well as other memory errors). Our results show that our compiler enables the servers to execute successfully through buffer overflow attacks to continue to correctly service user requests without security vulnerabilities.

School of Mathematics Computing Guide

Guide for computing in the School of Mathematics. Intended for new staff and PG students. Originally written by Anton Prowse from a number of earlier documents.