982 resultados para Figures


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Aims.We use observations and models of molecular D/H ratios to probe the physical conditions and chemical history of the gas and to differentiate between gas-phase and grain-surface chemical processing in star forming regions. Methods: As a follow up to previous observations of HDCO/H2CO and DCN/HCN ratios in a selection of low-mass protostellar cores, we have measured D2CO/H2CO and N2D^+/N2H+ ratios in these same sources. For comparison, we have also measured N2D^+/N2H+ ratios towards several starless cores and have searched for N2D+ and deuterated formaldehyde towards hot molecular cores (HMCs) associated with high mass star formation. We compare our results with predictions from detailed chemical models, and to other observations made in these sources. Results: Towards the starless cores and low-mass protostellar sources we have found very high N2D+ fractionation, which suggests that the bulk of the gas in these regions is cold and heavily depleted. The non-detections of N2D+ in the HMCs indicate higher temperatures. We did detect HDCO towards two of the HMCs, with abundances 1-3% of H2CO. These are the first detections of deuterated formaldehyde in high mass sources since Turner (1990) measured HDCO/H2CO and D2CO/H2CO towards the Orion Compact Ridge. Figures 1-5 are only available in electronic form at http://www.aanda.org

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We argue the results published by Bao-Quan Ai et al [Phys. Rev E 67, 022903 (2003)] on "correlated noise in a logistic growth model " are not correct. Their conclusion that for larger values of the correlation parameter, lambda, the cell population is peaked at x=0, which denotes the high extinction rate is also incorrect. We find the reverse behaviour corresponding to their results, that increasing lambda, promotes the stable growth of tumour cells. In particular, their results for steady-state probability, as a function of cell number, at different correlation strengths, presented in figures 1 and 2 show different behaviour than one would expect from the simple mathematical expression for the steady-state probability. Additionally, their interpretation at small values of cell number that the steady state probability increases as they increase the correlation parameter is also questionable. Another striking feature in their figures (1 and 3) is that for the same values of the parameter lambda and alpha, their simulation produces two different curves both qualitatively and quantitatively.

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The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

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In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

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In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

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In this paper, the analogue performance of a 65 nm node double gate Sol (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as f(T), and f(MAX). It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7 nm/decade. Analytical expressions, which reflect the dependence of f(T), and fMAX on extrinsic source, drain and gate resistances R-S, R-D and R-G have been derived. While R-D and R-S have equal effect on f(T), R-D appears to be more influential than R-S in reducing f(MAX). The sensitivity of f(MAX) to R-S and R-D. has been shown to be greater than to R-G. (c) 2006 Elsevier Ltd. All rights reserved.

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Self-report research suggests that much violence is triggered by perceived insults and disrespect. This may be particularly true in the context of a prison or another environment of acute deprivation, whereby individuals have little other recourse to means of reputation enhancement. This paper presents the findings of two studies conducted with prisoner volunteers inside a Category C (minimum security) prison in England. In the first study, the authors randomly assigned a sample of 89 prisoners to one of two conditions: the experimental group were asked to discuss times they have been disrespected by authority figures inside and outside the prison; the control group were asked more neutral questions. Both groups then completed several measures of cognitive beliefs, distortions, and hostile attribution biases. None of the measures differed across the two groups except the measure of excuse and justification acceptance. Controlling for other factors, the experimental group endorsed these rationalisations at a significantly higher rate than the control group. This finding suggests that raising the salience of disrespect - reminding prisoners of times they have been made to feel unworthy of consideration - may raise the risk that prisoners will engage in violence by providing prisoners with justifications or excuses for actions they might not otherwise endorse. These findings received some additional validation in the second study, a qualitative analysis of offender accounts of violence and aggression within the prison. Implications for reducing violence within prisons are discussed.